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2020 – today
- 2023
[c18]Padmapriya Duraisamy, Wei Xu, Scott Hare, Ravi Rajwar, David E. Culler, Zhiyi Xu, Jianing Fan, Christopher Kennelly, Bill McCloskey, Danijela Mijailovic, Brian Morris, Chiranjit Mukherjee, Jingliang Ren, Greg Thelen, Paul Turner, Carlos Villavieja, Parthasarathy Ranganathan, Amin Vahdat:
Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale. ASPLOS (3) 2023: 727-741
2010 – 2019
- 2015
- [j12]Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, Rajesh Kumar:
Haswell: A Family of IA 22 nm Processors. IEEE J. Solid State Circuits 50(1): 49-58 (2015) - [c17]Ravi Rajwar, Martin G. Dixon, Ronak Singhal:
Specialized Evolution of the General Purpose CPU. CIDR 2015 - 2014
- [j11]Per Hammarlund, Alberto J. Martinez, Atiq A. Bajwa, David L. Hill, Erik G. Hallnor, Hong Jiang, Martin G. Dixon, Michael Derr, Mikal Hunsaker, Rajesh Kumar, Randy B. Osborne, Ravi Rajwar, Ronak Singhal, Reynold D'Sa, Robert Chappell, Shiv Kaushik, Srinivas Chennupaty, Stéphan Jourdan, Steve Gunther, Thomas Piazza, Ted Burton:
Haswell: The Fourth-Generation Intel Core Processor. IEEE Micro 34(2): 6-20 (2014) - [c16]Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner:
Improving in-memory database index performance with Intel® Transactional Synchronization Extensions. HPCA 2014: 476-487 - 2013
- [c15]Richard M. Yoo, Christopher J. Hughes
, Konrad Lai, Ravi Rajwar:
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. SC 2013: 19:1-19:11 - 2012
- [c14]Ravi Rajwar:
In search of parallel dimensions. SPAA 2012: 37 - 2010
- [b2]Tim Harris, James R. Larus, Ravi Rajwar:
Transactional Memory, 2nd Edition. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2010, ISBN 978-3-031-00600-5
2000 – 2009
- 2008
- [j10]Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles:
Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation. IEEE Micro 28(1): 21-31 (2008) - 2007
- [c13]Craig B. Zilles, Ravi Rajwar:
Implications of False Conflict Rate Trends for Robust Software Transactional Memory. IISWC 2007: 15-24 - [c12]Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles:
Hardware atomicity for reliable software speculation. ISCA 2007: 174-185 - [c11]Craig B. Zilles, Ravi Rajwar:
Transactional memory and the birthday paradox. SPAA 2007: 303-304 - 2006
- [b1]James R. Larus, Ravi Rajwar:
Transactional Memory. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2006, ISBN 978-3-031-01719-3 - [j9]Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad Lai:
Scalable Load and Store Processing in Latency-Tolerant Processors. IEEE Micro 26(1): 30-39 (2006) - 2005
- [j8]J. Eliot B. Moss, Ravi Rajwar:
Atomicity as a First-Class System Provision. J. Univers. Comput. Sci. 11(5): 651-660 (2005) - [j7]Cliff B. Jones, David B. Lomet, Alexander B. Romanovsky, Gerhard Weikum, Alan D. Fekete, Marie-Claude Gaudel, Henry F. Korth, Rogério de Lemos, J. Eliot B. Moss, Ravi Rajwar, Krithi Ramamritham, Brian Randell, Luís E. T. Rodrigues:
The atomic manifesto: a story in four quarks. SIGMOD Rec. 34(1): 63-69 (2005) - [j6]Cliff B. Jones, David B. Lomet, Alexander B. Romanovsky, Gerhard Weikum, Alan D. Fekete, Marie-Claude Gaudel, Henry F. Korth, Rogério de Lemos, J. Eliot B. Moss, Ravi Rajwar, Krithi Ramamritham, Brian Randell, Luís E. T. Rodrigues:
The atomic manifesto: a story in four quarks. ACM SIGOPS Oper. Syst. Rev. 39(2): 41-46 (2005) - [c10]Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai:
Scalable Load and Store Processing in Latency Tolerant Processors. ISCA 2005: 446-457 - [c9]Ravi Rajwar, Maurice Herlihy, Konrad K. Lai:
Virtualizing Transactional Memory. ISCA 2005: 494-505 - [c8]Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upton, Konrad K. Lai:
The Impact of Performance Asymmetry in Emerging Multicore Architectures. ISCA 2005: 506-517 - 2004
- [j5]Ravi Rajwar, Alain Kägi, James R. Goodman:
Inferential Queueing and Speculative Push. Int. J. Parallel Program. 32(3): 225-258 (2004) - [j4]Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton:
Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance. IEEE Micro 24(6): 62-73 (2004) - [j3]Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
An analysis of a resource efficient checkpoint architecture. ACM Trans. Archit. Code Optim. 1(4): 418-444 (2004) - [c7]Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton:
Continual flow pipelines. ASPLOS 2004: 107-119 - [i1]Cliff B. Jones, David B. Lomet, Alexander B. Romanovsky, Gerhard Weikum, Alan D. Fekete, Marie-Claude Gaudel, Henry F. Korth, Rogério de Lemos, J. Eliot B. Moss, Ravi Rajwar, Krithi Ramamritham, Brian Randell, Luís E. T. Rodrigues:
The Atomic Manifesto: a Story in Four Quarks. Atomicity in System Design and Execution 2004 - 2003
- [j2]Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers. IEEE Micro 23(6): 11-19 (2003) - [j1]Ravi Rajwar, James R. Goodman:
Transactional Execution: Toward Reliable, High-Performance Multithreading. IEEE Micro 23(6): 117-125 (2003) - [c6]Ravi Rajwar, Alain Kägi, James R. Goodman:
Inferential queueing and speculative push for reducing critical communication latencies. ICS 2003: 273-284 - [c5]Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. MICRO 2003: 423- - 2002
- [c4]Ravi Rajwar, James R. Goodman:
Transactional lock-free execution of lock-based programs. ASPLOS 2002: 5-17 - 2001
- [c3]Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko H. Lipasti:
An Architectural Evaluation of Java TPC-W. HPCA 2001: 229-240 - [c2]Ravi Rajwar, James R. Goodman:
Speculative lock elision: enabling highly concurrent multithreaded execution. MICRO 2001: 294-305 - 2000
- [c1]Ravi Rajwar, Alain Kägi, James R. Goodman:
Improving the Throughput of Synchronization by Insertion of Delays. HPCA 2000: 168-179
Coauthor Index
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