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ORCID32nd RSP 2021: Paris, France
- IEEE International Workshop on Rapid System Prototyping, RSP 2021, Paris, France, October 14, 2021. IEEE 2021, ISBN 978-1-6654-6956-2
- Soobeom Kim, Seunghwan Cho, Eunhyeok Park, Sungjoo Yoo:
FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural Networks. 1-7 - Theo Soriano, David Novo, Pascal Benoit:
An FPGA-based Emulation Platform for Edge Computing Node Design Exploration. 8-14 - Théotime Bollengier, Loïc Lagadec, Ciprian Teodorov:
Prototyping FPGA through overlays. 15-21 - Nils Büscher, Daniel Gis, Johann-Peter Wolff, Christian Haubelt:
Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform. 22-28 - Kevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max E. Kramer, Clemens Reichmann:
Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation. 29-35 - Loïc France, Florent Bruguier, Maria Mushtaq, David Novo, Pascal Benoit:
Implementing Rowhammer Memory Corruption in the gem5 Simulator. 36-42 - Kevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli:
Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator. 43-49 - Felipe Göhring de Magalhães, Mahdi Nikdast, Fabiano Hessel, Odile Liboiron-Ladouceur
, Gabriela Nicolescu:
HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks. 50-56 - Harpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent:
Heterogeneous Logic Implementation for Adders in VTR. 57-63 - Bruno Ferres, Olivier Muller, Frédéric Rousseau:
Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. 64-70
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