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ORCIDACM Transactions on Architecture and Code Optimization (TACO), Volume 5
Volume 5, Number 1, May 2008
- Brad Calder, Dean M. Tullsen:
Editorial. 1:1 - Shashidhar Mysore, Banit Agrawal, Rodolfo Neuber, Timothy Sherwood
, Nisheeth Shrivastava, Subhash Suri:
Formulating and implementing profiling over adaptive ranges. 2:1-2:32 - Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, Todd C. Mowry:
Compiler and hardware support for reducing the synchronization of speculative threads. 3:1-3:33 - Jonathan A. Winter, David H. Albonesi:
Addressing thermal nonuniformity in SMT workloads. 4:1-4:28 - Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
Versatility of extended subwords and the matrix register file. 5:1-5:30 - Zhi Guo, Walid A. Najjar, Betul Buyukkurt:
Efficient hardware code generation for FPGAs. 6:1-6:26 - Thomas Kotzmann, Christian Wimmer, Hanspeter Mössenböck, Thomas Rodriguez, Kenneth B. Russell, David Cox:
Design of the Java HotSpot™ client compiler for Java 6. 7:1-7:32
Volume 5, Number 2, August 2008
- Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August:
Performance scalability of decoupled software pipelining. 8:1-8:25 - Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee:
Thermal monitoring mechanisms for chip multiprocessors. 9:1-9:33 - Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John:
Distilling the essence of proprietary workloads into miniature benchmarks. 10:1-10:33 - Vincenzo Catania, Maurizio Palesi, Davide Patti:
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. 11:1-11:33
Volume 5, Number 3, November 2008
- Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
Comparative evaluation of memory models for chip multiprocessors. 12:1-12:30 - Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev:
Reducing register pressure in SMT processors through L2-miss-driven early register release. 13:1-13:28 - Mojtaba Mehrara, Todd M. Austin:
Exploiting selective placement for low-cost memory protection. 14:1-14:24 - Hans Vandierendonck, André Seznec:
Speculative return address stack management revisited. 15:1-15:20
Volume 5, Number 4, March 2009
- Siddhartha Chhabra, Brian Rogers, Yan Solihin, Milos Prvulovic:
Making secure processors OS- and performance-friendly. 16:1-16:35 - Daniel A. Jiménez:
Generalizing neural branch prediction. 17:1-17:27 - Jinseong Jeon, Keoncheol Shin, Hwansoo Han:
Abstracting access patterns of dynamic memory using regular expressions. 18:1-18:28 - Ghassan Shobaki, Kent D. Wilken, Mark Heffernan:
Optimal trace scheduling using enumeration. 19:1-19:32
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