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ORCIDAlejandro Valero
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- affiliation: University of Zaragoza, Spain
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2020 – today
- 2024
[j13]Yamilka Toca-Díaz, Reynier Hernández Palacios, Ruben Gran Tejero, Alejandro Valero
:
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage. Microprocess. Microsystems 106: 105023 (2024)- 2023
- [c14]Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero:
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. DSD 2023: 138-145 - 2022
- [j12]Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni:
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. J. Syst. Archit. 128: 102553 (2022) - [c13]Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals:
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS 2022: 1-6 - [c12]Hugo Tárrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo:
Fast-track cache: a huge racetrack memory L1 data cache. ICS 2022: 23:1-23:12 - 2021
- [j11]Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez:
A learning experience toward the understanding of abstraction-level interactions in parallel applications. J. Parallel Distributed Comput. 156: 38-52 (2021) - [i1]Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia:
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. CoRR abs/2105.03859 (2021) - 2020
- [j10]Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero:
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. IEEE Access 8: 173276-173288 (2020)
2010 – 2019
- 2019
- [j9]Alejandro Valero, Francisco Candel, Darío Suárez Gracia, Salvador Petit, Julio Sahuquillo:
An Aging-Aware GPU Register File Design Based on Data Redundancy. IEEE Trans. Computers 68(1): 4-20 (2019) - [j8]Francisco Candel, Alejandro Valero, Salvador Petit, Julio Sahuquillo:
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance. IEEE Trans. Computers 68(10): 1442-1454 (2019) - [c11]Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals:
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2018
- [c10]Francisco Candel, Salvador Petit, Alejandro Valero, Julio Sahuquillo:
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache. Euro-Par 2018: 235-248 - 2017
- [j7]Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones:
On Microarchitectural Mechanisms for Cache Wearout Reduction. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 857-871 (2017) - [c9]Francisco Candel, Alejandro Valero, Salvador Petit, Darío Suárez Gracia, Julio Sahuquillo:
Exploiting Data Compression to Mitigate Aging in GPU Register Files. SBAC-PAD 2017: 57-64 - 2016
- [j6]Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones:
Enhancing the L1 Data Cache Design to Mitigate HCI. IEEE Comput. Archit. Lett. 15(2): 93-96 (2016) - 2015
- [j5]Alejandro Valero, Salvador Petit, Julio Sahuquillo, David R. Kaeli, José Duato:
A reuse-based refresh policy for energy-aware eDRAM caches. Microprocess. Microsystems 39(1): 37-48 (2015) - [j4]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Design of Hybrid Second-Level Caches. IEEE Trans. Computers 64(7): 1884-1897 (2015) - 2014
- [c8]Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo:
Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. HPCC/CSS/ICESS 2014: 19-26 - 2013
- [b1]Alejandro Valero:
Hybrid caches: design and data management. Polytechnic University of Valencia, Spain, 2013 - [c7]Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato:
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE 2013: 83-88 - [c6]Vicente Lorente, Alejandro Valero, Ramon Canal:
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. Euro-Par Workshops 2013: 454-464 - [c5]Alejandro Valero, Julio Sahuquillo, Salvador Petit, José Duato:
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. ICS 2013: 491-492 - 2012
- [j3]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Combining recency of information with selective random and a victim cache in last-level caches. ACM Trans. Archit. Code Optim. 9(3): 16:1-16:20 (2012) - [j2]Alejandro Valero, Salvador Petit, Julio Sahuquillo, Pedro López, José Duato:
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. IEEE Trans. Computers 61(9): 1231-1242 (2012) - [j1]Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato:
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1108-1117 (2012) - [c4]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Analyzing the optimal ratio of SRAM banks in hybrid caches. ICCD 2012: 297-302 - 2011
- [c3]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011: 214 - [c2]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato:
MRU-Tour-based Replacement Algorithms for Last-Level Caches. SBAC-PAD 2011: 112-119
2000 – 2009
- 2009
- [c1]Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato:
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009: 213-221
Coauthor Index
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