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2020 – today
- 2024
[j4]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda
, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C. IEEE J. Solid State Circuits 59(4): 1283-1292 (2024)- [c8]Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono:
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs. ISSCC 2024: 290-292 - 2022
- [j3]Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier. IEEE J. Solid State Circuits 57(10): 3094-3102 (2022) - [c7]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C. VLSI Technology and Circuits 2022: 134-135 - 2021
- [c6]Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. A-SSCC 2021: 1-3
2010 – 2019
- 2019
- [c5]Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. VLSI Circuits 2019: 210- - 2016
- [c4]Tomoya Ogawa, Katsuhiro Naito:
Development of Multi-hop Field Sensor Networks with Arduino Board. IIMSS 2016: 241-251 - 2014
- [j2]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. IEEE J. Solid State Circuits 49(1): 154-166 (2014) - 2013
- [c3]Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. ISSCC 2013: 212-213
2000 – 2009
- 2006
- [j1]Taku Ogura, Masahiro Hosoda, Tomoya Ogawa, Tamiyu Kato, Akihiko Kanda, Tomoyuki Fujisawa, Satoshi Shimizu, Masafumi Katsumata:
A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function. IEEE J. Solid State Circuits 41(11): 2589-2600 (2006) - 2004
- [c2]Tomoya Ogawa, Nobuhiro Inuzuka:
Similarity of Documents Using Reconfiguration of Thesaurus. KES 2004: 95-102 - 2002
- [c1]Ayato Noro, Tomoya Ogawa, Takuma Ohta, Kazuyuki Yamashita, Shigeki Miyaji, Mitue Den:
Performance of Adaptive Mesh Refinement Scheme for Hydrodynamics on Simulations of Expanding Supernova Envelope. ISHPC 2002: 207-218
Coauthor Index
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