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ORCIDMamidala Jagadesh Kumar
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2020 – today
- 2020
[j6]Aakash Kumar Jain
, Mamidala Jagadesh Kumar:
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study. IEEE Access 8: 137540-137548 (2020)
2010 – 2019
- 2017
- [j5]Shubham Sahay, Mamidala Jagadesh Kumar:
Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs. IEEE Access 5: 18918-18926 (2017) - [j4]Sindhu Ramaswamy, Mamidala Jagadesh Kumar:
Double gate symmetric tunnel FET: investigation and analysis. IET Circuits Devices Syst. 11(4): 365-370 (2017) - [c6]Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar:
DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions. VLSID 2017: 385-390 - 2012
- [c5]Tarun Kumar Agarwal, Mamidala Jagadesh Kumar:
Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model. VLSI Design 2012: 406-411 - 2010
- [c4]Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar:
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. VLSI Design 2010: 230-234
2000 – 2009
- 2007
- [c3]Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal:
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. VLSI Design 2007: 189-194 - 2004
- [j3]G. Venkateshwar Reddy, Mamidala Jagadesh Kumar:
Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. Microelectron. J. 35(9): 761-765 (2004) - [c2]Mamidala Jagadesh Kumar, Vinod Parihar:
A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. VLSI Design 2004: 827-831 - 2003
- [j2]Mamidala Jagadesh Kumar, Linga Reddy Cenkeramaddi:
2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI. Microelectron. Reliab. 43(7): 1145-1149 (2003) - [c1]Mamidala Jagadesh Kumar, D. Venkateshrao:
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. VLSI Design 2003: 489-492 - 2002
- [j1]Mamidala Jagadesh Kumar, Vikram Verma:
Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET. IEEE Trans. Reliab. 51(3): 367-370 (2002)
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