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2020 – today

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2024
[j26]
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Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
HW-FUTEX: Hardware-Assisted Futex Syscall. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 16-29 (2024)
[c101]
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Lars Nolte, Tim Twardzik, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
Hardware Assist for Linux IPC on an FPGA Platform. CF 2024
[c100]
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Tim Twardzik, Lars Nolte, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
HASIIL: Hardware-Assisted Scheduling to Improve IPC Latency in Linux. CF 2024
[c99]
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Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer:
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE 2024: 1-6
[c98]
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Anmol Surhonne, Manuel Wensauer, Florian Maurer, Thomas Wild, Andreas Herkersdorf:
XCS with dynamic sized experience replay for memory constrained applications. GECCO Companion 2024: 1807-1814
[c97]
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Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. PDP 2024: 52-59
[i5]
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  - journals/corr/abs-2407-08621
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Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. CoRR abs/2407.08621 (2024)
2023
[c96]
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Klajd Zyla, Florian Maurer, Thomas Wild, Andreas Herkersdorf:
CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. ARCS 2023: 215-229
[c95]
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Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Clara Kowalsky, Thomas Wild, Andreas Herkersdorf:
HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. DAC 2023: 1-6
[c94]
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Anmol Surhonne, Florian Maurer, Thomas Wild, Andreas Herkersdorf:
LCT-DER: Learning Classifier Table with Dynamic-Sized Experience Replay for Run-time SoC Performance-Power Optimization. GECCO Companion 2023: 331-334
[c93]
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Anmol Surhonne, Florian Maurer, Thomas Wild, Andreas Herkersdorf:
LCT-TL : Learning Classifier Table (LCT) with Transfer Learning for runtime SoC performance-power optimization. MCSoC 2023: 73-80
[c92]
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Marco Liess, Julian Demicoli, Tobias Tiedje, Matthias Lohrmann, Matthias Nickel, M. Luniak, Dimitrios A. Prousalis, Thomas Wild, Ronald Tetzlaff, Diana Göhringer, Christian Mayr, Karlheinz Bock, Sebastian Steinhorst, Andreas Herkersdorf:
X-MAPE: Extending 6G-Connected Self-Adaptive Systems with Reflexive Actions. NFV-SDN 2023: 163-167
[c91]
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Franz Biersack, Kilian Holzinger, Henning Stubbe, Thomas Wild, Georg Carle, Andreas Herkersdorf:
Priority-aware Inter-Server Receive Side Scaling. PDP 2023: 51-58
[c90]
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Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. VLSI-SoC 2023: 1-6
2022
[j25]
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Mark Sagi, Nguyen Anh Vu Doan, Nael Fasfous, Thomas Wild, Andreas Herkersdorf:
Fine-Grained Power Modeling of Multicore Processors Using FFNNs. Int. J. Parallel Program. 50(2): 243-266 (2022)
[j24]
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Zarrar Khan, Mengqi Zhao, Chris R. Vernon, Thomas Wild, Brinda Yarlagadda:
rmap: An R package to plot and compare tabular data on customizable maps across scenarios and time. J. Open Source Softw. 7(77): 4015 (2022)
[c89]
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Anmol Surhonne, Nguyen Anh Vu Doan, Florian Maurer, Thomas Wild, Andreas Herkersdorf:
GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization. ARCS 2022: 271-285
[c88]
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Kilian Holzinger, Franz Biersack, Henning Stubbe, Angela Gonzalez Mariño, Abdoul Kane, Francesc Fons, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle:
SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications. NOMS 2022: 1-6
[c87]
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Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
GLS Tracing: Gem5-based Low-intrusive Software Tracing. NorCAS 2022: 1-6
2021
[j23]
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Sven Rheindt, Sebastian Maier, Nora Pohle, Lars Nolte, Oliver Lenke, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf:
DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. Int. J. Parallel Program. 49(4): 506-540 (2021)
[j22]
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Akshay Srivatsa, Mostafa Mansour, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf:
DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. Int. J. Parallel Program. 49(4): 570-599 (2021)
[j21]
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Mengqi Zhao, Matthew Binsted, Thomas Wild, Zarrar Khan, Brinda Yarlagadda, Gokul Iyer, Chris R. Vernon, Pralit Patel, Sílvia da Silva, Katherine V. Calvin:
plutus: An R package to calculate electricity investments and stranded assets from the Global Change Analysis Model (GCAM). J. Open Source Softw. 6(65): 3212 (2021)
[j20]
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Akshay Srivatsa, Nael Fasfous, Nguyen Anh Vu Doan, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf:
Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. Microprocess. Microsystems 87: 104384 (2021)
[j19]
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs. Microprocess. Microsystems 87: 104385 (2021)
[c86]
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Kilian Holzinger, Henning Stubbe, Franz Biersack, Angela Gonzalez Mariño, Abdoul Kane, Francisco Fons Lluis, Haigang Zhang, Thomas Wild, Andreas Herkersdorf, Georg Carle:
Precise real-time monitoring of time-critical flows. CoNEXT 2021: 489-490
[c85]
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Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jörg Henkel, Andreas Herkersdorf:
Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. DATE 2021: 1685-1690
[c84]
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Oliver Lenke, Richard Petri, Thomas Wild, Andreas Herkersdorf:
PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. MEMSYS 2021: 9:1-9:6
2020
[j18]
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Mark Sagi, Nguyen Anh Vu Doan, Martin Rapp, Thomas Wild, Jörg Henkel, Andreas Herkersdorf:
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3152-3164 (2020)
[j17]
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  - journals/todaes/HuMMWHS20
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Yong Hu, Marcel Mettler, Daniel Mueller-Gritschneder, Thomas Wild, Andreas Herkersdorf, Ulf Schlichtmann:
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. ACM Trans. Design Autom. Electr. Syst. 25(5): 44:1-44:27 (2020)
[c83]
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Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Temur Sabirov, Tim Twardzik, Thomas Wild, Andreas Herkersdorf:
X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs. ARCS 2020: 109-123
[c82]
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  - conf/ieem/DoanSFNWH20
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Nguyen Anh Vu Doan, Akshay Srivatsa, Nael Fasfous, Sebastian Nagel, Thomas Wild, Andreas Herkersdorf:
On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. IEEM 2020: 984-988
[c81]
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Sven Rheindt, Temur Sabirov, Oliver Lenke, Thomas Wild, Andreas Herkersdorf:
X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. MEMSYS 2020: 178-193
[c80]
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  - conf/norchip/KoenenDWH20
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. NorCAS 2020: 1-7
[c79]
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Akshay Srivatsa, Sebastian Nagel, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
HyVE: A Hybrid Voting-based Eviction Policy for Caches. NorCAS 2020: 1-7
[c78]
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  - conf/pdp/OeldemannBWH20
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Andreas Oeldemann, Franz Biersack, Thomas Wild, Andreas Herkersdorf:
Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution. PDP 2020: 46-53
[c77]
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Mark Sagi, Nguyen Anh Vu Doan, Nael Fasfous, Thomas Wild, Andreas Herkersdorf:
Fine-Grained Power Modeling of Multicore Processors Using FFNNs. SAMOS 2020: 186-199

2010 – 2019

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2019
[c76]
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Dominik Scholz, Andreas Oeldemann, Fabien Geyer, Sebastian Gallenmüller, Henning Stubbe, Thomas Wild, Andreas Herkersdorf, Georg Carle:
Cryptographic Hashing in P4 Data Planes. ANCS 2019: 1-6
[c75]
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. ARCS 2019: 31-44
[c74]
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Michael Vonbun, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Network Coding in Networks-on-Chip with Lossy Links. ARCS 2019: 308-321
[c73]
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  - conf/codes/RamboKESKDMMMSY19
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Eberle A. Rambo, Thawra Kadeed, Rolf Ernst, Minjun Seo, Fadi J. Kurdahi, Bryan Donyanavard, Caio Batista de Melo, Biswadip Maity, Kasra Moazzemi, Kenneth Michael Stewart, Saehanseul Yi, Amir M. Rahmani, Nikil D. Dutt, Florian Maurer, Nguyen Anh Vu Doan, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf:
The information processing factory: a paradigm for life cycle management of dependable systems. CODES+ISSS 2019: 20:1-20:2
[c72]
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Nguyen Anh Vu Doan, Max Koenen, Thomas Wild, Andreas Herkersdorf:
Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. CANDAR Workshops 2019: 201-207
[c71]
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Mark Sagi, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Multicore Power Estimation using Independent Component Analysis Based Modeling. MCSoC 2019: 38-45
[c70]
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Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf:
NEMESYS: near-memory graph copy enhanced system-software. MEMSYS 2019: 3-18
[c69]
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Michael Vonbun, Adrian Schiechel, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs. NOCS 2019: 6:1-6:8
[c68]
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf:
Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs. NOCS 2019: 20:1-20:2
[c67]
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Akshay Srivatsa, Sven Rheindt, Dirk Gabriel, Thomas Wild, Andreas Herkersdorf:
CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures. SAMOS 2019: 18-33
[c66]
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Sven Rheindt, Sebastian Maier, Florian Schmaus, Thomas Wild, Wolfgang Schröder-Preikschat, Andreas Herkersdorf:
SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. SAMOS 2019: 212-225
[c65]
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Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Poças, Thomas Wild, Andreas Herkersdorf:
Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. SoCC 2019: 406-411
2018
[j16]
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  - journals/pieee/MostlSEDNRKWSH18
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Mischa Möstl, Johannes Schlatow, Rolf Ernst, Nikil D. Dutt, Ahmed Nassar, Amir-Mohammad Rahmani, Fadi J. Kurdahi, Thomas Wild, Armin Sadighi, Andreas Herkersdorf:
Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS. Proc. IEEE 106(9): 1543-1567 (2018)
[c64]
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Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf:
CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms. ARCS 2018: 139-152
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Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild:
BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates. ASAP 2018: 1-9
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Armin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mück, Ahmed Nassar, Amir M. Rahmani, Thomas Wild, Nikil D. Dutt, Rolf Ernst, Andreas Herkersdorf, Fadi J. Kurdahi:
Design methodologies for enabling self-awareness in autonomous systems. DATE 2018: 1532-1537
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Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf:
FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. FPL 2018: 178-185
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Thomas Goldbrunner, Thomas Wild, Andreas Herkersdorf:
Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models. PATMOS 2018: 32-38
2017
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Philipp Wagner, Thomas Wild, Andreas Herkersdorf:
DiaSys: Improving SoC insight through on-chip diagnosis. J. Syst. Archit. 75: 120-132 (2017)
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Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich:
Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. 77: 72-82 (2017)
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Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf:
Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. ARCS 2017: 234-247
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Lin Li, Philipp Wagner, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf:
A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. DATE 2017: 322-325
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Ihsen Alouani, Thomas Wild, Andreas Herkersdorf, Smaïl Niar:
Adaptive Reliability for Fault Tolerant Multicore Systems. DSD 2017: 538-542
[c56]
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Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild:
A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression. PDCAT 2017: 400-406
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Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf:
Region based cache coherence for tiled MPSoCs. SoCC 2017: 286-291
2016
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Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016)
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Stefan Rosch, Holm Rauchfuss, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf:
MPSoC application resilience by hardware-assisted communication virtualization. Microelectron. Reliab. 61: 11-16 (2016)
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Philipp Wagner, Thomas Wild, Andreas Herkersdorf:
DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. ARCS 2016: 197-209
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Michael Vonbun, Thomas Wild, Andreas Herkersdorf:
Estimation of End-to-End Packet Error Rates for NoC Multicasts. ARCS 2016: 363-374
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Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf:
Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions. DSD 2016: 454-462
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Philipp Wagner, Lin Li, Thomas Wild, Albrecht Mayer, Andreas Herkersdorf:
What happens on an MPSoC stays on an MPSoC - unfortunately! ISIC 2016: 1-2
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Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf, Thomas Wild:
Hardware acceleration of signature matching through multi-layer transition bit masking. ITNAC 2016: 217-224
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Lin Li, Philipp Wagner, Ramesh Ramaswamy, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf:
A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. SCOPES 2016: 180-189
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Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf:
TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. ISC 2016: 39-58
[i4]
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Philipp Wagner, Thomas Wild, Andreas Herkersdorf:
Improving SoC Insight Through On-Chip Diagnosis. CoRR abs/1607.04549 (2016)
2015
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Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang:
Adaptive multi-layer techniques for increased system dependability. it Inf. Technol. 57(3): 149-158 (2015)
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Andre Oliver Richter, Christian Herber, Thomas Wild, Andreas Herkersdorf:
Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance. J. Syst. Archit. 61(10): 592-599 (2015)
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Andre Oliver Richter, Christian Herber, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf:
A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV. CLOUD 2015: 950-957
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Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker:
Fault-tolerant communication in invasive networks on chip. AHS 2015: 1-8
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Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS 2015: 186-198
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Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf:
Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. DATE 2015: 61-66
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Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf:
A hardware-based multi-objective thread mapper for tiled manycore architectures. ICCD 2015: 459-462
[c42]
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P. Parayil Mana Damodaran, Aurang Zaib, Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf:
Sharer status-based caching in tiled multiprocessor systems-on-chip. SpringSim (HPS) 2015: 67-74
2014
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops 2014: 1-8
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Andre Oliver Richter, Christian Herber, Holm Rauchfuss, Thomas Wild, Andreas Herkersdorf:
Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing. ARCS 2014: 171-182
[c39]
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Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Krohnert, Jochen Reisinger:
System integration - The bridge between More than Moore and More Moore. DATE 2014: 1-9
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Stefan Wallentowitz, Stefan Rosch, Thomas Wild, Andreas Herkersdorf, Volker Wenzel, Jörg Henkel:
Dependable task and communication migration in tiled manycore system-on-chip. FDL 2014: 1-8
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Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf:
Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN). HPCC/CSS/ICESS 2014: 693-700
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Christian Herber, Andre Oliver Richter, Thomas Wild, Andreas Herkersdorf:
A network virtualization approach for performance isolation in controller area network (CAN). RTAS 2014: 215-224
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Walter Stechele, Thomas Wild:
ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering. VDE Verlag / IEEE Xplore 2014, ISBN 978-3-8007-3579-2 [contents]
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Aurang Zaib, Prashanth Raju, Thomas Wild, Andreas Herkersdorf:
A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. CoRR abs/1405.2917 (2014)
2013
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Felix Miller, Thomas Wild, Andreas Herkersdorf:
Virtualized and fault-tolerant inter-layer-links for 3D-ICs. Microprocess. Microsystems 37(8-A): 823-835 (2013)
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. 6(2): 8:1-8:14 (2013)
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Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf:
HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. ARCS 2013: 280-291
[c34]
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Karol Kozak, Sandra Kaestner, Thomas Wild, Andreas Vonderheit, Benjamin Misselwitz, Ulrike Kutay, Gabor Csucs:
New Algorithm for Analysis of Off-target Effects in siRNA Screens. BIOINFORMATICS 2013: 253-260
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Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD 2013: 761-768
[c32]
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Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib:
Potentials and Challenges for Multi-Core Processors in Robotic Applications. GI-Jahrestagung 2013: 2749-2764
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Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker:
Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops 2013: 153-162
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Stefan Wallentowitz, Philipp Wagner, Michael Tempelmeier, Thomas Wild, Andreas Herkersdorf:
Open Tiled Manycore System-on-Chip. CoRR abs/1304.5081 (2013)
2012
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Andreas Herkersdorf, Hans-Ulrich Michel, Holm Rauchfuss, Thomas Wild:
Multicore Enablement for Automotive Cyber Physical Systems. it Inf. Technol. 54(6): 280-287 (2012)
[j6]
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Andreas Lankes, Thomas Wild, Stefan Wallentowitz, Andreas Herkersdorf:
Benefits of selective packet discard in networks-on-chip. ACM Trans. Archit. Code Optim. 9(2): 12:1-12:21 (2012)
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Holm Rauchfuss, Thomas Wild, Andreas Herkersdorf:
Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation. ARCS Workshops 2012: 263-274
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Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe:
Invasive manycore architectures. ASP-DAC 2012: 193-200
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Felix Miller, Thomas Wild, Andreas Herkersdorf:
TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. DSD 2012: 374-381
[c27]
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Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib:
An integrated simulation framework for invasive computing. FDL 2012: 209-216
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Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf:
A framework for Open Tiled Manycore System-On-Chip. FPL 2012: 535-538
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops 2012: 234-241
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Roman Plyaskin, Thomas Wild, Andreas Herkersdorf:
System-level software performance simulation considering out-of-order processor execution. ISSoC 2012: 1-7
2011
[j5]
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Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf:
Advanced Packet Segmentation and Buffering Algorithms in Network Processors. Trans. High Perform. Embed. Archit. Compil. 4: 334-353 (2011)
[c23]
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Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf:
Accelerating collective communication in message passing on manycore System-on-Chip. ICSAMOS 2011: 9-16
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Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld:
Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. Multiprocessor System-on-Chip 2011: 57-87
2010
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Kimon Karras, Thomas Wild, Andreas Herkersdorf:
A folded pipeline network processor architecture for 100 Gbit/s networks. ANCS 2010: 2
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Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf:
An Application-Aware Load Balancing Strategy for Network Processors. HiPEAC 2010: 156-170
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Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig:
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. NOCS 2010: 17-24
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Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf:
FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. Dynamically Reconfigurable Systems 2010: 355-374

2000 – 2009

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2009
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Andreas Lankes, Thomas Wild, Andreas Herkersdorf:
Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. DSD 2009: 255-262
2008
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Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf:
A Processing Path Dispatcher in Network Processor MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1335-1345 (2008)
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Andreas Lankes, Thomas Wild, Johannes Zeppenfeld:
System Level Simulation of Autonomic SoCs with TAPES. ARCS 2008: 9-22
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Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
A Hardware Packet Re-Sequencer Unit for Network Processors. ARCS 2008: 85-97
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Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf:
Buffer allocation for advanced packet segmentation in Network Processors. ASAP 2008: 221-226
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Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
Network processors. FPL 2008: 352
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Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
FlexPath NP - A network processor architecture with flexible processing paths. SoC 2008: 1-6
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Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann:
Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design. ISVLSI 2008: 16-21
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Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf:
Improving memory subsystem performance in network processors with smart packet segmentation. ICSAMOS 2008: 210-217
2007
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Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf:
Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. J. Syst. Archit. 53(10): 703-718 (2007)
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Andreas Lankes, Thomas Wild, Johannes Zeppenfeld:
Power Estimation of Time Variant SoCs with TAPES. DSD 2007: 261-264
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Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf:
A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. ISVLSI 2007: 259-264
2006
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Jürgen Foag, Thomas Wild:
Queuing algorithm for speculative Network Processors. Int. J. High Perform. Comput. Netw. 4(5/6): 241-247 (2006)
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Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf:
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. DATE 2006: 248-253
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Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf:
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. ICSAMOS 2006: 152-159
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Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild:
Reconfigurable Processing Units vs. Reconfigurable Interconnects. Dynamically Reconfigurable Architectures 2006
2005
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Thomas Wild, Andreas Herkersdorf, Gyoo-Yeong Lee:
TAPES - Trace-based architecture performance evaluation with SystemC. Des. Autom. Embed. Syst. 10(2-3): 157-179 (2005)
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Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild:
FlexPath NP: a network processor concept with application-driven flexible processing paths. CODES+ISSS 2005: 279-284
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Jürgen Foag, Thomas Wild:
Predictive processing architecture extension for network processors. ICECS 2005: 1-4
2004
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Jürgen Foag, Thomas Wild:
Queuing Algorithm for Speculative Network Processors. HPCS 2004: 3-8
2003
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Thomas Wild:
Ein rekursives Verfahren zur Abbildung und zum Scheduling von Prozess-Graphen mit Kontrollabhängigkeiten. Technical University Munich, Germany, 2003, pp. 1-142
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Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos:
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. DSD 2003: 98-103
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Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer:
Mapping and Scheduling for Architecture Exploration of Networking SoCs. VLSI Design 2003: 376-381
2002
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Jürgen Foag, Nuria Pazos, Thomas Wild, Winthir Brunnbauer:
Self-Adaptive Parallel Processing Architecture For High-speed Networking. HPCS 2002: 45-52
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Jürgen Foag, Thomas Wild, Nuria Pazos, Winthir Brunnbauer:
Predictive methodology for high-performance networking. ISCC 2002: 169-174

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