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ORCIDJanakiraman Viraraghavan
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2020 – today
- 2024
[j9]S. Ashwin Balagopal
, Janakiraman Viraraghavan, Balaji Vijayakumar:
Input-Conditioned Quantisation for ENOB Improvement in CIM ADC Columns Targeting Large-Length Partial Sums. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 2971-2975 (2024)- 2023
- [j8]Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan:
Geometric Programming Approach to Glitch Minimization via Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1988-2001 (2023) - [j7]Alfred Festus Davidson, Janakiraman Viraraghavan:
Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection. IEEE Trans. Educ. 66(1): 83-93 (2023) - 2021
- [c5]Balaji Vijayakumar, Janakiraman Viraraghavan:
An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter. ISCAS 2021: 1-5 - 2020
- [j6]Koduru Revanth, Janakiraman Viraraghavan:
Statistical compact model extraction for skew-normal distributions. IET Circuits Devices Syst. 14(5): 576-585 (2020) - [c4]S. Ashwin Balagopal, Janakiraman Viraraghavan:
Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study. ISCAS 2020: 1-5
2010 – 2019
- 2018
- [j5]Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. IEEE J. Solid State Circuits 53(3): 949-960 (2018) - 2016
- [j4]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016) - [c3]Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2 - 2012
- [j3]Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts:
Statistical Compact Model Extraction: A Neural Network Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1920-1924 (2012) - 2010
- [j2]Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan:
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1056-1069 (2010)
2000 – 2009
- 2008
- [j1]Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan:
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electron. 4(3): 301-319 (2008) - [c2]Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur:
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672 - [c1]Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind:
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691
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