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2020 – today
- 2024
[c13]Heyu Ren, Liangjian Lyu, Binbin Chen, Chuanjin Richard Shi:
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. CICC 2024: 1-2- 2023
- [c12]Qingzhen Wang, Wenxian Gu, Hengchang Bi, Liangjian Lyu, Deli Qiao, Xing Wu:
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces. ASICON 2023: 1-4 - [c11]Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, Chuanjin Richard Shi:
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. A-SSCC 2023: 1-3 - [c10]Renze Gan, Liangjian Lyu, Chuanjin Richard Shi:
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. ESSCIRC 2023: 5-8 - [c9]Zijian Zhang, Q. Li, Zuoyuan Dong, Wanting Wang, S. T. Lai, Xin Yang, Fang Liang, Chaolun Wang, C. Luo, Liangjian Lyu, Z. Li, J. M. Xu, Xing Wu:
Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes. IRPS 2023: 1-5 - [c8]Hao Jiang, Jiapei Zheng, Yunzhengmao Wang
, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu:
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS 2023: 1-5 - 2022
- [j5]Haohan Wangxu, Liangjian Lyu, Hengchang Bi, Xing Wu:
Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip. Sensors 22(10): 3934 (2022) - [c7]Renze Gan, Liangjian Lyu, Geng Mu, Chuanjin Richard Shi:
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC 2022: 1-2 - 2021
- [c6]Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, Chuanjin Richard Shi:
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC 2021: 1-2 - 2020
- [j4]Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70: 51-59 (2020) - [j3]Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, Chuanjin Richard Shi:
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55(5): 1386-1400 (2020) - [j2]Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi:
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14(4): 811-824 (2020) - [j1]Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi:
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 831-835 (2020) - [c5]Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi:
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [c4]Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC 2019: 13-14 - [c3]Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi:
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS 2019: 1-4 - [c2]Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi:
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS 2019: 1-4 - 2018
- [c1]Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi:
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC 2018: 142-144
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last updated on 2024-08-05 21:19 CEST by the dblp team
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