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2020 – today
- 2022
[c22]James Perretta, Andrew DeOrio, Arjun Guha
, Jonathan Bell:
On the use of mutation analysis for evaluating student test suite quality. ISSTA 2022: 263-275- 2021
- [c21]Michael Ball, Andrew DeOrio, Justin Hsia, Adam Blank:
Teaching TAs to Teach: Strategies for TA Training. SIGCSE 2021: 461-462 - 2020
- [c20]Amy Baer, Andrew DeOrio:
A Longitudinal View of Gender Balance in a Large Computer Science Program. SIGCSE 2020: 23-29 - [c19]Michael Ball, Justin Hsia, Heather Pon-Barry, Andrew DeOrio, Adam Blank:
Teaching TAs To Teach: Strategies for TA Training. SIGCSE 2020: 477-478
2010 – 2019
- 2019
- [c18]Amir Kamil, James Juett, Andrew DeOrio:
Gender-balanced TAs from an Unbalanced Student Body. SIGCSE 2019: 300-306 - 2018
- [j5]Max O. Smith, Andrew Giugliano, Andrew DeOrio:
Long Term Effects of Pair Programming. IEEE Trans. Educ. 61(3): 187-194 (2018) - [i1]Edmond Cunningham, Dana Schlegel, Andrew DeOrio:
Explainable Genetic Inheritance Pattern Prediction. CoRR abs/1812.00259 (2018) - 2015
- [j4]Biruk W. Mammo, Valeria Bertacco, Andrew DeOrio, Ilya Wagner:
Post-Silicon Validation of Multiprocessor Memory Consistency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 1027-1037 (2015) - [c17]Rico Angell, Ben Oztalay, Andrew DeOrio:
A Topological Approach to Hardware Bug Triage. MTV 2015: 20-25 - 2013
- [c16]Andrew DeOrio, Qingkun Li, Matthew Burgess, Valeria Bertacco:
Machine learning-based anomaly detection for post-silicon bug diagnosis. DATE 2013: 491-496 - 2012
- [b1]Andrew DeOrio:
Correct Communication in Multi-core Processors. University of Michigan, USA, 2012 - [j3]Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David T. Blaauw, Jin Hu, Gregory K. Chen:
A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 726-739 (2012) - [c15]Andrew DeOrio, Jialin Li, Valeria Bertacco:
Bridging pre- and post-silicon debugging with BiPeD. ICCAD 2012: 95-100 - [c14]Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco:
Comprehensive online defect diagnosis in on-chip networks. VTS 2012: 44-49 - 2011
- [j2]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Gate-Level Simulation with GPU Computing. ACM Trans. Design Autom. Electr. Syst. 16(3): 30:1-30:26 (2011) - [c13]Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco:
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment. PACT 2011: 298-309 - [c12]Andrew DeOrio, Konstantinos Aisopos, Valeria Bertacco, Li-Shiuan Peh:
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips. DAC 2011: 912-917 - [c11]Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco:
Post-silicon bug diagnosis with inconsistent executions. ICCAD 2011: 755-761 - [c10]Rawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco:
Functional correctness for CMP interconnects. ICCD 2011: 352-359 - 2010
- [c9]Andrew DeOrio, Valeria Bertacco:
Electronic design automation for social networks. DAC 2010: 621-622
2000 – 2009
- 2009
- [j1]Andrew DeOrio, Adam Bauserman, Valeria Bertacco, Beth Isaksen:
Inferno: Streamlining Verification With Inferred Semantics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 728-741 (2009) - [c8]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
Event-driven gate-level simulation with GP-GPUs. DAC 2009: 557-562 - [c7]Andrew DeOrio, Valeria Bertacco:
Human computing for EDA. DAC 2009: 621-622 - [c6]David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester:
Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817 - [c5]David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw:
A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26 - [c4]Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco:
GCS: High-performance gate-level simulation with GPGPUs. DATE 2009: 1332-1337 - [c3]Andrew DeOrio, Ilya Wagner, Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. HPCA 2009: 405-416 - 2008
- [c2]Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Post-silicon verification for cache coherence. ICCD 2008: 348-355 - 2007
- [c1]Andrew DeOrio, Adam Bauserman, Valeria Bertacco:
Chico: An On-chip Hardware Checker for Pipeline Control Logic. MTV 2007: 91-97
Coauthor Index
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