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ORCIDGrace Zgheib
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2020 – today
- 2022
[j2]Stefan Nikolic
, Grace Zgheib, Paolo Ienne:
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. 15(4): 37:1-37:33 (2022)- 2021
- [c17]Grace Zgheib, Yu Shen Lu, Ilya Ganusov:
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. FPL 2021: 327-333 - 2020
- [c16]Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov:
Architectural Enhancements in Intel® Agilex™ FPGAs. FPGA 2020: 140-149 - [c15]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA 2020: 150-160 - [c14]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL 2020: 153-161
2010 – 2019
- 2019
- [c13]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL 2019: 31-37 - 2017
- [b1]Grace Zgheib:
Leading the Blind - Automated Transistor-Level Modeling for FPGA Architects. EPFL, Switzerland, 2017 - [c12]Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA 2017: 135-140 - [c11]Grace Zgheib, Paolo Ienne:
Evaluating FPGA clusters under wide ranges of design parameters. FPL 2017: 1-8 - [c10]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - 2016
- [c9]Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA 2016: 80-89 - [c8]Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. FPT 2016: 181-184 - 2015
- [j1]Grace Zgheib, Iyad Ouaiss:
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. J. Circuits Syst. Comput. 24(3): 1550039:1-1550039:19 (2015) - [c7]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - [c6]Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. FPT 2015: 80-87 - [c5]Haidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya:
An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components. IRI 2015: 225-228 - 2014
- [c4]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - 2013
- [c3]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c2]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - 2011
- [c1]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne:
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246
Coauthor Index
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