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ORCIDTsutomu Hoshino
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2000 – 2009
- 2001
[c16]Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino:
A Cellular Automata System with FPGA. FCCM 2001: 120-129- [c15]Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano:
A Music Synthesizer on FPGA. FPL 2001: 377-387 - 2000
- [c14]Yohei Hori
, Minenobu Seki, Reijer Grimbergen, Tsutomu Maruyama, Tsutomu Hoshino:
A Shogi Processor with a Field Programmable Gate Array. Computers and Games 2000: 297-314 - [c13]Tsutomu Maruyama, Tsutomu Hoshino:
A C to HDL Compiler for Pipeline Processing on FPGAs. FCCM 2000: 101-112 - [c12]Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino:
A Co-processor System with a Virtex FPGA for Evolutionary Computation. FPL 2000: 240-249 - [c11]Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino:
High Speed Computation of Lattice gas Automata with FPFA. FPL 2000: 801-804
1990 – 1999
- 1999
- [c10]Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi:
An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. AAAI/IAAI 1999: 182-187 - [c9]Yoshiki Yamaguchi, Tsutomu Maruyama, Tsutomu Hoshino:
High Speed Hardware Computation of Co-evolution Models. ECAL 1999: 566-574 - [c8]Tsutomu Maruyama, Masaaki Takagi, Tsutomu Hoshino:
Hardware Implementation Techniques for Recursive Calls and Loops. FPL 1999: 450-455 - [c7]Tsutomu Maruyama, Tsutomu Hoshino:
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing. FPL 1999: 514-519 - 1998
- [j6]Tsutomu Hoshino, Daisuke Mitsumoto, Tohru Nagano:
Fractal Fitness Landscape and Loss of Robustness in Evolutionary Robot Navigation. Auton. Robots 5(2): 199-213 (1998) - [c6]Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino:
A Field-Programmable Gate-Array System for Evolutionary Computation. FPL 1998: 356-365 - [c5]Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12 - 1996
- [c4]Isamu Kajitani, Tsutomu Hoshino, Masaya Iwata, Tetsuya Higuchi:
Variable Length Chromosome GA for Evolvable Hardware. International Conference on Evolutionary Computation 1996: 443-447 - 1994
- [j5]Yukihiko Toquenaga, Isamu Kajitani, Tsutomu Hoshino:
Egrets of a Feather Flock Together. Artif. Life 1(4): 391-411 (1994)
1980 – 1989
- 1988
- [j4]Tsutomu Hoshino, Robert Hiromoto, Satoshi Sekiguchi, S. Majima:
Mapping schemes of the particle-in-cell method implemented on the PAX computer. Parallel Comput. 9(1): 53-75 (1988) - 1987
- [j3]Tsutomu Hoshino, Tomonori Shirakawa, Keiichi Tsuboi:
Mesh-connected parallel computer PAX for scientific applications. Parallel Comput. 5(3): 363-371 (1987) - 1986
- [j2]Tsutomu Hoshino:
An Invitation to the World of PAX. Computer 19(5): 68-79 (1986) - 1985
- [c3]Tsutomu Hoshino, Takeshi Kamimura, Toshihiro Iida, Tomonori Shirakawa:
Parallelized ADI Scheme Using GECR (Gauss-Elimination-Cyclic-Reduction) Method and Implementation of Navier-Stokes Equation in the PAX computer. ICPP 1985: 426-433 - 1984
- [c2]Tsutomu Hoshino, Tomonori Shirakawa, Yoshio Oyanagi, Kiyo Takenouchi, Toshio Kawai:
Super Freedom Simulator PAX. VLSI Engineering 1984: 39-51 - 1983
- [j1]Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Jun'ichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada:
PACS: A Parallel Microprocessor Array for Scientific Calculations. ACM Trans. Comput. Syst. 1(3): 195-221 (1983) - [c1]Tsutomu Hoshino, Tomonori Shirakawa, Takeshi Kamimura, Takahisa Kageyama, Kiyo Takenouchi, Hidehiko Abe, Satoshi Sekiguchi, Yoshio Oyanagi, Toshio Kawai:
Highly Parallel Processor Array "PAX" for Wide Scientific Applications. ICPP 1983: 95-105
Coauthor Index
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