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ORCIDKarthikeyan Lingasubramanian
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2020 – today
- 2020
[j5]Varsha Kakkara, Karthi Balasubramanian
, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan:
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. PeerJ Comput. Sci. 6: e250 (2020)
2010 – 2019
- 2019
- [c10]Karthi Balasubramanian, B. Yamuna, Salija P, Karthikeyan Lingasubramanian, Deepak Mishra:
Effect of sign-bit-flipping trojan on turbo coded communication systems. ICDCN 2019: 502-505 - 2018
- [c9]A. R. Aravind, S. R. Kesavaraman, Karthi Balasubramanian, B. Yamuna, Karthikeyan Lingasubramanian:
Effect of hardware Trojans on the performance of a coded communication system. ICCE 2018: 1-6 - [c8]Karthikeyan Lingasubramanian, Ranveer Kumar, Nagendra Babu Gunti, Thomas H. Morris:
Study of hardware trojans based security vulnerabilities in cyber physical systems. ICCE 2018: 1-6 - 2017
- [j4]Gunti Nagendra Babu, Karthikeyan Lingasubramanian:
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits. Integr. 59: 233-242 (2017) - [c7]Nagendra Babu Gunti, Karthikeyan Lingasubramanian:
Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR. iNIS 2017: 99-104 - [c6]Nagendra Babu Gunti, Karthikeyan Lingasubramanian:
Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme. iNIS 2017: 105-110 - 2014
- [c5]Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian:
Realizing a security aware triple modular redundancy scheme for robust integrated circuits. VLSI-SoC 2014: 1-6 - 2011
- [j3]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectron. Reliab. 51(2): 485-501 (2011) - [c4]Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS 2011: 214-225
2000 – 2009
- 2009
- [j2]Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja:
Probabilistic Error Modeling for Nano-Domain Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 55-65 (2009) - [c3]Karthikeyan Lingasubramanian, Sanjukta Bhanja:
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. VLSI Design 2009: 485-490 - [i1]Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja:
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis. CoRR abs/0906.3282 (2009) - 2007
- [c2]Karthikeyan Lingasubramanian, Sanjukta Bhanja:
Probabilistic maximum error modeling for unreliable logic circuits. ACM Great Lakes Symposium on VLSI 2007: 223-226 - 2006
- [j1]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) - 2005
- [c1]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591
Coauthor Index
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