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ORCIDGabriele Saucier
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2000 – 2009
- 2002
[c62]L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier:
E-Design Based on the Reuse Paradigm. DATE 2002: 214-220- [c61]Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier:
Who Owns the Platform? DATE 2002: 238 - 2000
- [c60]Helena Krupnova, Gabriele Saucier:
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. FPL 2000: 68-77 - [c59]Helena Krupnova, Gabriele Saucier:
FPGA Technology Snapshot: Current Devices and Design Tools. IEEE International Workshop on Rapid System Prototyping 2000: 200-
1990 – 1999
- 1999
- [c58]Helena Krupnova, Gabriele Saucier:
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. DATE 1999: 587- - [c57]Helena Krupnova, Gabriele Saucier:
Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. FPGA 1999: 251 - [c56]Helena Krupnova, Gabriele Saucier:
Hierarchical Interactive Approach to Partition Large Designs into FPGAs. FPL 1999: 101-110 - [c55]Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping 1999: 128-133 - 1998
- [j18]Daniel R. Brasen, Gabriele Saucier:
Using cone structures for circuit partitioning into FPGA packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7): 592-600 (1998) - [c54]S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier:
Timing Driven Floorplanning on Programmable Hierarchical Targets. FPGA 1998: 85-92 - [c53]Helena Krupnova, B. Behnam, Gabriele Saucier:
Block and IP Wrapping for Efficient Design on FPGAs (Abstract). FPGA 1998: 256 - [c52]Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier:
A Knowledge-Based System for Prototyping on FPFAs. FPL 1998: 89-98 - [c51]Helena Krupnova, Dinh Duc Anh Vu, Gabriele Saucier, Michel Boubal:
Real Time Prototyping Method and a Case Study. International Workshop on Rapid System Prototyping 1998: 13-18 - [c50]Bernard Laurent, Gilles Bosco, Gabriele Saucier:
Fast Arithmetic on Xilinx 5200 FPGA. VLSI Design 1998: 322-325 - 1997
- [c49]Helena Krupnova, Ali Abbara, Gabriele Saucier:
A Hierarchy-Driven FPGA Partitioning Method. DAC 1997: 522-525 - [c48]Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
Synthesis and Floorplanning for Large Hierarchical FPGAs. FPGA 1997: 105-111 - [c47]Bernard Laurent, Gilles Bosco, Gabriele Saucier:
Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. FPL 1997: 462-471 - 1995
- [c46]Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Efficient synthesis of fault-tolerant controllers. ED&TC 1995: 593 - [c45]P. Brahic, Régis Leveugle, Gabriele Saucier:
Design of defect-tolerant scan chains for MCMs with an active substrate. DFT 1995: 252-260 - 1994
- [j17]Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn:
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers 43(12): 1398-1406 (1994) - [c44]Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier:
Design Automation Tools for FPGA Design (Panel). DAC 1994: 676 - [c43]Régis Leveugle, Raphaël Rochet, Gabriele Saucier:
Alternative Approaches to Fault Detection in FSMs. DFT 1994: 271-279 - [c42]T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier:
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC 1994: 14-18 - [c41]Daniel R. Brasen, Gabriele Saucier:
FPGA Partitioning for Critical Paths. EDAC-ETC-EUROASIC 1994: 99-103 - [c40]D. Jacquet, Gabriele Saucier:
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. EDAC-ETC-EUROASIC 1994: 256-260 - [c39]C. Safinia, Régis Leveugle, Gabriele Saucier:
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC 1994: 349-353 - 1993
- [j16]Margot Karam, Gabriele Saucier:
Functional versus random test generation for sequential circuits. J. Electron. Test. 4(1): 33-41 (1993) - [j15]Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier:
Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 913-925 (1993) - [j14]Gabriele Saucier, Pierre Abouzeid:
Lexicographical expressions of Boolean functions with application to multilevel synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1642-1654 (1993) - [c38]Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT 1993: 9-16 - [c37]Régis Leveugle, Raphaël Rochet, Gabriele Saucier, L. Martinez, C. Pitot:
A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS 1993: 502-511 - [c36]Gabriele Saucier, Daniel R. Brasen, J. P. Hiol:
Partitioning with cone structures. ICCAD 1993: 236-239 - [c35]Régis Leveugle, X. Delord, Gabriele Saucier:
Influence of Error Correlations on the Signature Analysis Aliasing. ICCD 1993: 584-587 - [c34]D. Jacquet, Gabriele Saucier:
Design of a dedicated neural network on silicon: application to optical character recognition. VLSI 1993: 169-178 - [e1]Gabriele Saucier, Jacques Trilhe:
Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992. IFIP Transactions A-22, North-Holland 1993, ISBN 0-444-81479-5 [contents] - 1992
- [j13]Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe:
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors. Computer 25(4): 29-39 (1992) - [j12]Laurent Gerbaux, Gabriele Saucier:
Automatic synthesis of large Moore sequencers. Integr. 13(3): 259-281 (1992) - [c33]T. Besson, H. Bouzouzou, M. Crastes, Ion Floricica, Gabriele Saucier:
Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. ICCD 1992: 163-167 - [c32]Laurent Gerbaux, Régis Leveugle, Gabriele Saucier:
Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits 1992: 47-59 - [c31]H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier:
Specification and Synthesis of Communicating Finite State Machines. Synthesis for Control Dominated Circuits 1992: 91-102 - [c30]Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier:
ASYL: A Control Driven RTL Synthesis System using Library Blocks. Synthesis for Control Dominated Circuits 1992: 275-291 - [c29]Pierre Abouzeid, Régis Leveugle, Gabriele Saucier:
Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits 1992: 335-343 - 1991
- [c28]M. Crastes, K. Sakouti, Gabriele Saucier:
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. DAC 1991: 93-98 - [c27]T. Michel, Régis Leveugle, Gabriele Saucier:
A New Approach to Control Flow Checking Without Program Modification. FTCS 1991: 334-343 - [c26]Christopher Duff, Gabriele Saucier:
State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. ICCAD 1991: 222-225 - [c25]Margot Karam, Régis Leveugle, Gabriele Saucier:
Hierarchical Test Generation Based on Delayed Propagation. ITC 1991: 739-747 - [c24]X. Delord, Gabriele Saucier:
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. ITC 1991: 936-945 - [c23]J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette:
A Customizable Neural Processor for Distributed Neural Network. VLSI 1991: 167-176 - 1990
- [j11]Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers 39(4): 419-425 (1990) - [c22]Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot:
Multilevel Synthesis Minimizing the Routing Factor. DAC 1990: 365-368 - [c21]Gabriele Saucier, Pascal Sicard, Laurent Bouchet:
Multi-level synthesis on PALs. EURO-DAC 1990: 542-546 - [c20]Gabriele Saucier, Christopher Duff, Franck Poirot:
State assignment of controllers for optimal area implementation. EURO-DAC 1990: 547-551 - [c19]Régis Leveugle, T. Michel, Gabriele Saucier:
Design of microprocessors with built-in on-line test. FTCS 1990: 450-456 - [c18]J. Ouali, Gabriele Saucier:
Silicon compiler for neuro-ASICs. IJCNN 1990: 557-561
1980 – 1989
- 1989
- [c17]Gabriele Saucier, Christopher Duff, Franck Poirot:
State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. DAC 1989: 321-326 - [c16]Gabriele Saucier, Régis Leveugle, Pierre Abouzeid:
A channelless layout for multilevel synthesis with compiled cells. ICCD 1989: 35-38 - [c15]Régis Leveugle, Gabriele Saucier:
Concurrent checking in dedicated controllers. ICCD 1989: 124-127 - [c14]J. Ouali, Gabriele Saucier:
A flexible architecture for neural networks. ICCD 1989: 483-486 - [c13]Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC 1989: 355-363 - [c12]Michel Crastes de Paulet, Margot Karam, Gabriele Saucier:
Testability Expertise and Test Planning from High-Level Specifications. ITC 1989: 692-699 - 1988
- [j10]Ghislaine Thuau, Gabriele Saucier:
Optimized Layout of MOS Cells. IEEE Trans. Computers 37(1): 79-87 (1988) - [c11]Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe:
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. GI Jahrestagung (2) 1988: 75-91 - 1987
- [j9]Gabriele Saucier, Michel Crastes de Paulet, Pascal Sicard:
ASYL: A Rule-Based System for Controller Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1088-1097 (1987) - [c10]E. F. M. Kouka, Gabriele Saucier:
An Application of Exploratory Data Analysis Techniques to Floorplan Design. DAC 1987: 654-658 - 1986
- [c9]E. Dupont, Jeanne Idt, Gabriele Saucier:
A Rule-Based System for the Optimal State Assignment of Controllers. FJCC 1986: 915-923 - 1985
- [c8]Gabriele Saucier, Ghislaine Thuau:
Systematic and optimized layout of MOS cells. DAC 1985: 53-61 - 1984
- [j8]Robert Cuykendall, Antun Domic, William H. Joyner, Stephen C. Johnson, Steven H. Kelem, Dennis McBride, Jack Mostow, John E. Savage, Gabriele Saucier:
Design synthesis in VLSI and software engineering. J. Syst. Softw. 4(1): 7-12 (1984) - [c7]Gabriele Saucier, Catherine Bellon:
VLSI test expertise system using a control flow model. DAC 1984: 497-503 - [c6]Catherine Bellon, Gabriele Saucier:
CADOC : A System for Computer Aided Functional Test. ITC 1984: 680-689 - 1982
- [j7]Catherine Bellon, Gabriele Saucier:
Protection Against External Errors in a Dedicated System. IEEE Trans. Computers 31(4): 311-317 (1982) - [c5]Catherine Bellon, A. Liothin, Sylvain Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman:
Automatic generation of microprocessor test programs. DAC 1982: 566-573 - [c4]Philippe Basset, Gabriele Saucier:
Top down design and testability of VLSI circuits. DAC 1982: 851-857 - 1981
- [c3]Catherine Bellon, Gabriele Saucier, José-Maria Gobbi:
Hardware description levels and test for complex circuits. DAC 1981: 213-219
1970 – 1979
- 1978
- [j6]Chantal Robach, Gabriele Saucier:
Dynamic Testing of Control Units. IEEE Trans. Computers 27(7): 617-623 (1978) - 1976
- [j5]Chantal Robach, Gabriele Saucier, J. Lebrun:
Processor Testability and Design Consequences. IEEE Trans. Computers 25(6): 645-652 (1976) - [c2]M. Moalla, Gabriele Saucier, Joseph Sifakis, Marianthi Zachariades:
A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. ISCA 1976: 20-27 - 1975
- [j4]Chantal Robach, Gabriele Saucier:
Diversified Test Methods for Local Control Units. IEEE Trans. Computers 24(5): 562-567 (1975) - [c1]Bernard Courtois, Gabriele Saucier:
On balancing hardware-firmware for designing a fault-tolerant computers' series. MICRO (2) 1975: 1-5 - 1972
- [j3]Gabriele Saucier:
State Assignment of Asynchronous Sequential Machines Using Graph Techniques. IEEE Trans. Computers 21(3): 282-288 (1972) - [j2]Gabriele Saucier:
Next-State Equations of Asynchronous Sequential Machines. IEEE Trans. Computers 21(4): 397-399 (1972) - 1970
- [b2]Gabrièle Saucier:
Codage des automates asynchrones. Joseph Fourier University, Grenoble, France, 1970
1960 – 1969
- 1967
- [j1]Gabrièle Saucier:
Encoding of Asynchronous Sequential Networks. IEEE Trans. Electron. Comput. 16(3): 365-369 (1967) - 1964
- [b1]Gabrièle Saucier:
Codage des tableaux d'états des systèmes séquentiels asynchrones. Joseph Fourier University, Grenoble, France, 1964
Coauthor Index
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