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2020 – today
- 2024
[c9]Martin Cochet, Karthik Swaminathan, Erik Jens Loscalzo, Joseph Zuckerman, Maico Cassel dos Santos, Davide Giri, Alper Buyuktosunoglu, Tianyu Jia, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. ISCA 2024: 801-817- [c8]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - [c7]Erik Jens Loscalzo, Martin Cochet, Joseph Zuckerman, Samira Zalias, Michael Lekas, Stephen Cahill, Tianyu Jia, Karthik Swaminathan, Maico Cassel dos Santos, Davide Giri, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, David Brooks, Gu-Yeon Wei, Luca P. Carloni, Pradip Bose, Kenneth L. Shepard:
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j3]Gabriele Tombesi
, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni:
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. IEEE Des. Test 40(6): 64-75 (2023) - [c6]Thierry Tambe, Jeff Zhang, Coleman Hooper, Tianyu Jia, Paul N. Whatmough, Joseph Zuckerman, Maico Cassel dos Santos, Erik Jens Loscalzo, Davide Giri, Kenneth L. Shepard, Luca P. Carloni, Alexander M. Rush, David Brooks, Gu-Yeon Wei:
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. ISSCC 2023: 342-343 - 2022
- [c5]Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC 2022: 269-272 - [c4]Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD 2022: 20:1-20:9
2010 – 2019
- 2014
- [c3]Maico Cassel dos Santos, Luigi Carro:
An adaptive low-power receiver architecture for IEEE 802.15.4 standard. I2MTC 2014: 600-603
2000 – 2009
- 2008
- [j2]Érika F. Cota, Fernanda Gusmão de Lima Kastensmidt, Maico Cassel, Marcos Hervé, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski:
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip. IEEE Trans. Computers 57(9): 1202-1215 (2008) - 2007
- [j1]Arthur Pereira Frantz, Maico Cassel, Fernanda Lima Kastensmidt, Érika F. Cota, Luigi Carro:
Crosstalk- and SEU-Aware Networks on Chips. IEEE Des. Test Comput. 24(4): 340-350 (2007) - [c2]Érika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski:
Redefining and testing interconnect faults in Mesh NoCs. ITC 2007: 1-10 - 2006
- [c1]Maico Cassel, Fernanda Lima Kastensmidt:
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. IOLTS 2006: 139-144
Coauthor Index
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last updated on 2024-10-18 20:33 CEST by the dblp team
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