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ORCIDKazuei Hironaka
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2020 – today
- 2023
[j5]M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106(11): 1783-1795 (2023)- [j4]Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano:
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106(12): 1997-2005 (2023) - 2022
- [j3]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. 105-D(12): 2008-2018 (2022) - [c19]Kensuke Iizuka, Haruna Takagi, Aika Kamei
, Kazuei Hironaka, Hideharu Amano:
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS 2022: 1-6 - [c18]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC 2022: 45-52 - 2021
- [j2]Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano:
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. 104-D(8): 1321-1331 (2021) - [j1]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [c17]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT 2021: 46-50 - [c16]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS 2021: 1-6 - [c15]Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano:
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR 2021: 95-101 - 2020
- [c14]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c13]Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) 2020: 277-281 - [c12]Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano:
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC 2020: 25-26
2010 – 2019
- 2019
- [c11]Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano:
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL 2019: 417-418 - [c10]Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano:
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. HEART 2019: 15:1-15:4 - [c9]Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano:
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC 2019: 328-333 - [c8]Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano:
Multi-FPGA Management on Flow-in-Cloud Prototype System. SNPD 2019: 443-448 - 2018
- [c7]Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano:
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. ARC 2018: 142-150 - 2012
- [c6]Toru Katagiri, Kazuei Hironaka, Hideharu Amano:
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array. NBiS 2012: 826-831 - 2011
- [c5]Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami:
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC 2011: 230-241 - [c4]Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano:
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. FPT 2011: 1-4 - [c3]Masayuki Kimura, Kazuei Hironaka, Hideharu Amano:
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. FPT 2011: 1-8 - [c2]Kazuei Hironaka, Hideharu Amano:
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. ReConFig 2011: 404-409 - 2010
- [c1]Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT 2010: 349-352
Coauthor Index
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