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2020 – today
- 2024
[c13]Abhishek Tyagi, Reiley Jeyapaul, Chuteng Zhou, Paul N. Whatmough, Yuhao Zhu:
Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. ISPASS 2024: 96-108- [i2]Abhishek Tyagi, Reiley Jeyapaul, Chuteng Zhu, Paul N. Whatmough, Yuhao Zhu:
Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. CoRR abs/2404.09317 (2024) - 2020
- [i1]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian
, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
2010 – 2019
- 2019
- [j7]Abhishek Rhisheekesan, Reiley Jeyapaul, Aviral Shrivastava:
Control Flow Checking or Not? (for Soft Errors). ACM Trans. Embed. Comput. Syst. 18(1): 11:1-11:25 (2019) - 2018
- [c12]Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul:
LASER: A hardware/software approach to accelerate complicated loops on CGRAs. DATE 2018: 1069-1074 - 2017
- [j6]Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava:
Protecting Caches from Soft Errors: A Microarchitect's Perspective. ACM Trans. Embed. Comput. Syst. 16(4): 93:1-93:28 (2017) - [j5]Reiley Jeyapaul, Roberto Flores, Alfonso Ávila, Aviral Shrivastava:
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 547-555 (2017) - 2016
- [c11]Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee, Aviral Shrivastava:
gemV: A validated toolset for the early exploration of system reliability. ASAP 2016: 159-163 - 2015
- [j4]Jared Pager, Reiley Jeyapaul, Aviral Shrivastava:
A Software Scheme for Multithreading on CGRAs. ACM Trans. Embed. Comput. Syst. 14(1): 19:1-19:26 (2015) - [c10]Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava:
Guidelines to design parity protected write-back L1 data cache. DAC 2015: 24:1-24:6 - 2014
- [j3]Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee:
UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability. IEEE Trans. Parallel Distributed Syst. 25(1): 254-263 (2014) - [c9]Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu:
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. DAC 2014: 13:1-13:6 - 2013
- [j2]Reiley Jeyapaul, Aviral Shrivastava:
Enabling energy efficient reliability in embedded systems through smart cache cleaning. ACM Trans. Design Autom. Electr. Syst. 18(4): 53:1-53:25 (2013) - 2012
- [c8]Kyoungwoo Lee, Aviral Shrivastava, Reiley Jeyapaul:
Soft errors: the hardware-software interface. CODES+ISSS 2012: 577-578 - 2011
- [c7]Reiley Jeyapaul, Aviral Shrivastava:
Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. CASES 2011: 105-114 - [c6]Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula:
Enabling Multithreading on CGRAs. ICPP 2011: 255-264 - [c5]Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee:
UnSync: A Soft Error Resilient Redundant Multicore Architecture. ICPP 2011: 632-641 - 2010
- [j1]Reiley Jeyapaul, Aviral Shrivastava:
Code Transformations for TLB Power Reduction. Int. J. Parallel Program. 38(3-4): 254-276 (2010) - [c4]Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul:
Cache vulnerability equations for protecting data in embedded processor caches from soft errors. LCTES 2010: 143-152 - [c3]Reiley Jeyapaul, Aviral Shrivastava:
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. SCOPES 2010: 2
2000 – 2009
- 2009
- [c2]Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava:
Code Transformations for TLB Power Reduction. VLSI Design 2009: 413-418 - 2008
- [c1]Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek:
SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. ASP-DAC 2008: 776-782
Coauthor Index
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last updated on 2024-08-05 21:22 CEST by the dblp team
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