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ORCIDChang-Hyo Yu
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2020 – today
- 2024
[c14]Chang-Hyo Yu, Hyo-Eun Kim, Sungho Shin, Kyeongryeol Bong, Hyunsuk Kim, Yoonho Boo, Jaewan Bae, Minjae Kwon, Karim Charfi, Jinseok Kim, Hongyun Kim, Myeongbo Shim, Changsoo Ha, Wongyu Shin, Jae-Sung Yoon, Miock Chi, Byungjae Lee, Sungpill Choi, Donghan Kim, Jeongseok Woo, Seokju Yoon, Hyunje Jo, Hyunho Kim, Hyun-Seok Heo, Young-Jae Jin, Jiun Yu, Jaehwan Lee, Hyunsung Kim, Minhoo Kang, Seokhyeon Choi, Seung-Goo Kim, Myung-Hoon Choi, Jungju Oh, Yunseong Kim, Haejoon Kim, Sangeun Je, Junhee Ham, Juyeong Yoon, Jaedon Lee, Seonhyeok Park, Youngseob Park, Jaebong Lee, Boeui Hong, Jaehun Ryu, Hyunseok Ko, Kwanghyun Chung, Jongho Choi, Sunwook Jung, Yashael Faith Arthanto, Jonghyeon Kim, Heejin Cho, Hyebin Jeong, Sungmin Choi, Sujin Han, Junkyu Park, Kwangbae Lee, Sung-Il Bae, Jaeho Bang, Kyeong-Jae Lee, Yeongsang Jang, Jungchul Park, Sanggyu Park, Jueon Park, Hyein Shin, Sunghyun Park, Jinwook Oh:
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications. ISSCC 2024: 42-44
2010 – 2019
- 2013
- [c13]Yongha Park, Chang-Hyo Yu, Kilwhan Lee, Hyunsuk Kim, Youngeun Park, Chun-Ho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park:
72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application. ISSCC 2013: 160-161 - 2011
- [j8]Hong-Yun Kim, Chang-Hyo Yu, Lee-Sup Kim:
A Memory-Efficient Unified Early Z-Test. IEEE Trans. Vis. Comput. Graph. 17(9): 1286-1294 (2011) - [j7]Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 525-537 (2011)
2000 – 2009
- 2009
- [j6]Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. Comput. Graph. 33(5): 625-637 (2009) - [j5]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, Lee-Sup Kim:
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1369-1382 (2009) - 2008
- [j4]Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, Yun-Gu Lee, HyunWook Park, Jong Beom Ra, Lee-Sup Kim:
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. IEEE J. Solid State Circuits 43(5): 1247-1259 (2008) - [j3]Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1929-1938 (2008) - [c12]Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. CICC 2008: 367-370 - [c11]Jae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu, Lee-Sup Kim:
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. CICC 2008: 539-542 - 2007
- [j2]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. IEEE J. Solid State Circuits 42(10): 2257-2269 (2007) - [c10]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. CICC 2007: 579-582 - [c9]Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. ISCAS 2007: 765-768 - [c8]Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, HyunWook Park, Lee-Sup Kim:
A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. ISSCC 2007: 276-602 - 2006
- [j1]Donghyun Kim, Kyusik Chung, Chang-Hyo Yu, Chun-Ho Kim, Inho Lee, Jaewan Bae, Young-Jun Kim, Jae-Hyeon Park, Sungbeen Kim, Yong-Ha Park, Nak Hee Seong, Jin-Aeon Lee, Jaehong Park, Stephen Oh, Seh-Woong Jeong, Lee-Sup Kim:
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. IEEE J. Solid State Circuits 41(1): 71-84 (2006) - [c7]Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim:
An efficient texture cache for programmable vertex shaders. ISCAS 2006 - [c6]Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim:
Vertex cache of programmable geometry processor for mobile multimedia application. ISCAS 2006 - [c5]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. ISSCC 2006: 1606-1615 - 2005
- [c4]Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. ISCAS (5) 2005: 4574-4577 - 2004
- [c3]Chang-Hyo Yu, Lee-Sup Kim:
An adaptive spatial filter for early depth test. ISCAS (2) 2004: 137-140 - 2003
- [c2]Inho Lee, Joung-Youn Kim, Yeon-Ho Im, Yunseok Choi, Hyunchul Shin, Chang-Young Han, Donghyun Kim, Hyoungjoon Park, Young-Il Seo, Kyusik Chung, Chang-Hyo Yu, Kanghyup Chun, Lee-Sup Kim:
A hardware-like high-level language based environment for 3D graphics architecture exploration. ISCAS (2) 2003: 512-515 - [c1]Chang-Hyo Yu, Lee-Sup Kim:
A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter. ISCAS (2) 2003: 724-727
Coauthor Index
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