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ORCIDMartin Radetzki
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- affiliation: University of Stuttgart, Germany
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2020 – today
- 2023
[c62]Shuang Liu
, Martin Radetzki:
Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming. MCSoC 2023: 332-339- 2021
- [c61]Jie Hou, Martin Radetzki:
Comprehensive modeling and evaluation of Network-on-Chip performability. MBMV 2021: 1-12
2010 – 2019
- 2019
- [j15]Manuel Strobel, Martin Radetzki:
Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design. ACM Trans. Embed. Comput. Syst. 18(5): 43:1-43:25 (2019) - [c60]Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers:
Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS 2019: 121-124 - [c59]Jie Hou, Martin Radetzki:
A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms. FDL 2019: 1-7 - [c58]Manuel Strobel, Martin Radetzki:
A Backend Tool for the Integration of Memory Optimizations into Embedded Software. FDL 2019: 1-7 - [c57]Jens Rudolf, Manuel Strobel, Joscha Benz, Christian Haubelt, Martin Radetzki, Oliver Bringmann:
Automated Sensor Firmware Development - Generation, Optimization, and Analysis. MBMV 2019: 1-12 - [c56]Jie Hou, Qi Han, Martin Radetzki:
A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. MCSoC 2019: 164-171 - [c55]Manuel Strobel, Martin Radetzki:
Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems. MCSoC 2019: 347-353 - 2018
- [c54]Jie Hou, Martin Radetzki:
Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. PDP 2018: 609-616 - 2017
- [j14]Manuel Strobel, Marcus Eggenberger, Martin Radetzki:
Low power memory allocation and mapping for area-constrained systems-on-chips. EURASIP J. Embed. Syst. 2017: 2 (2017) - [j13]Gert Schley, Atefe Dalirsani, Marcus Eggenberger, Nadereh Hatami, Hans-Joachim Wunderlich, Martin Radetzki:
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. IEEE Trans. Computers 66(5): 848-861 (2017) - [c53]Leandro Gil, Martin Radetzki:
Semi-symbolic operational computation for robust control system design. MMAR 2017: 779-784 - [c52]Manuel Strobel, Martin Radetzki:
Hybrid instruction set simulation for fast and accurate memory access profiling. WISES 2017: 23-28 - 2016
- [j12]Gert Schley, Ibrahim Ahmed, Muhammad Afzal, Martin Radetzki:
Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Comput. Electr. Eng. 51: 195-206 (2016) - [c51]Leandro Gil, Martin Radetzki:
Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. DATE 2016: 499-504 - [c50]Marcus Eggenberger, Manuel Strobel, Martin Radetzki:
Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. PDP 2016: 763-770 - 2015
- [c49]Hans-Joachim Wunderlich, Martin Radetzki:
Multi-Layer Test and Diagnosis for Dependable NoCs. NOCS 2015: 5:1-5:8 - [c48]Gert Schley, Martin Radetzki:
Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. PDP 2015: 379-386 - [c47]Marcus Eggenberger, Martin Radetzki:
Optimal memory selection for low power embedded systems. WISES 2015: 11-16 - 2014
- [j11]Martin Radetzki, Axel Jantsch:
Editorial introduction - Special issue on languages, models and model based design for embedded systems. Des. Autom. Embed. Syst. 18(1-2): 61-62 (2014) - [c46]Atefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich:
On Covering Structural Defects in NoCs by Functional Tests. ATS 2014: 87-92 - [c45]Leandro Gil, Martin Radetzki:
SystemC AMS power electronic modeling with ideal instantaneous switches. FDL 2014: 1-8 - [c44]Bastian Haetzer, Martin Radetzki:
A comparison of parallel systemc simulation approaches at RTL. FDL 2014: 1-8 - [c43]Bastian Haetzer, Martin Radetzki:
Asynchronous parallel simulation with transaction events. ICSAMOS 2014: 242-249 - 2013
- [j10]Martin Radetzki, Chaochao Feng, Xueqian Zhao, Axel Jantsch:
Methods for fault tolerance in networks-on-chip. ACM Comput. Surv. 46(1): 8:1-8:38 (2013) - [j9]Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Tiberiu Seceleanu, Martin Radetzki, Hannu Tenhunen:
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. J. Electron. Test. 29(3): 431-452 (2013) - [j8]Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen:
Optimal placement of vertical connections in 3D Network-on-Chip. J. Syst. Archit. 59(7): 441-454 (2013) - [j7]Weiyun Lu, Martin Radetzki:
Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Microprocess. Microsystems 37(2): 115-128 (2013) - [c42]Jean-Philippe Babau, Martin Radetzki:
Platform based design. FDL 2013: 1 - [c41]Marcus Eggenberger, Martin Radetzki:
Fine grained adaptive simulation with application to NoCs. FDL 2013: 1-8 - [c40]Bastian Haetzer, Martin Radetzki:
Systemc transaction level modeling with transaction events. FDL 2013: 1-6 - [c39]Frank Oppenheimer, Martin Radetzki:
Simulation analysis and validation. FDL 2013: 1 - [c38]Adán Kohler, Martin Radetzki:
Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. GreenCom/iThings/CPScom 2013: 77-85 - [c37]Marcus Eggenberger, Martin Radetzki:
Scalable parallel simulation of networks on chip. NOCS 2013: 1-8 - [c36]Gert Schley, Nikolaos Batzolis, Martin Radetzki:
Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. PDP 2013: 454-461 - 2012
- [j6]Rauf Salimi Khaligh, Martin Radetzki:
Semantics and efficient simulation of accuracy-adaptive TLMs. Des. Autom. Embed. Syst. 16(3): 1-29 (2012) - [c35]Adán Kohler, Martin Radetzki, Philipp Gschwandtner, Thomas Fahringer:
Low-Latency Collectives for the Intel SCC. CLUSTER 2012: 346-354 - [c34]Adán Kohler, Juan Manuel Castillo-Sanchez, Joachim Gross, Martin Radetzki:
Minimal MPI as programming interface for multicore System-on-Chips. FDL 2012: 127-134 - [c33]Adán Kohler, Martin Radetzki:
Optimized Reduce for Mesh-Based NoC Multiprocessors. IPDPS Workshops 2012: 904-913 - [c32]Adán Kohler, Martin Radetzki:
Latency-optimized Collectives for High Performance on Intel's Single-chip Cloud Computer. MARC@RWTH 2012: 7-12 - 2011
- [c31]Weiyun Lu, Martin Radetzki:
Efficient Fault Simulation of SystemC Designs. DSD 2011: 487-494 - [c30]Bastian Haetzer, Gert Schley, Rauf Salimi Khaligh, Martin Radetzki:
Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. WESE 2011: 1-8 - [c29]Martin Radetzki:
Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. EUC 2011: 33-40 - [c28]Bastian Haetzer, Martin Radetzki:
A case study on message-based discrete event simulation for Transaction Level Modeling. FDL 2011: 1-8 - [c27]Rauf Salimi Khaligh, Martin Radetzki:
A metamodel and semantics for transaction level modeling. FDL 2011: 1-8 - [c26]Gert Schley, Martin Radetzki:
Optimal distribution of privileged nodes in networks-on-chip. WISES 2011: 87-92 - [p1]Martin Radetzki, Adán Kohler:
Cost-Based Deflection Routing for Intelligent NoC Switches. Solutions on Embedded Systems 2011: 77-90 - 2010
- [j5]Gert Schley, Martin Radetzki, Adán Kohler:
Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). it Inf. Technol. 52(4): 201-208 (2010) - [j4]Adán Kohler, Gert Schley, Martin Radetzki:
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 883-896 (2010) - [c25]Rauf Salimi Khaligh, Martin Radetzki:
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. DATE 2010: 1183-1188 - [c24]Rauf Salimi Khaligh, Martin Radetzki:
A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. FDL 2010: 130-135
2000 – 2009
- 2009
- [c23]Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto:
Test exploration and validation using transaction level models. DATE 2009: 1250-1253 - [c22]Adán Kohler, Martin Radetzki:
A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. FDL 2009: 1-4 - [c21]Rauf Salimi Khaligh, Martin Radetzki:
Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. IESS 2009: 149-158 - [c20]Adán Kohler, Martin Radetzki:
Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. MBMV 2009: 207-216 - [c19]Adán Kohler, Martin Radetzki:
Fault-tolerant architecture and deflection routing for degradable NoC switches. NOCS 2009: 22-31 - [c18]Martin Radetzki, Adán Kohler:
An intelligent deflection router for networks-on-chip. WISES 2009: 57-62 - [e1]Martin Radetzki:
Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL'08, September 23-25, 2008, Stuttgart, Germany. Lecture Notes in Electrical Engineering 36, 2009 [contents] - 2008
- [c17]Martin Radetzki, Rauf Salimi Khaligh:
Accuracy-Adaptive Simulation of Transaction Level Models. DATE 2008: 788-791 - [c16]Rauf Salimi Khaligh, Martin Radetzki:
A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. FDL 2008: 37-42 - [c15]Rauf Salimi Khaligh, Martin Radetzki:
Adaptive Interconnect Models for Transaction-Level Simulation. FDL (Selected Papers) 2008: 149-165 - [c14]Weining Hao, Martin Radetzki:
A data traffic efficient H.264 deblocking IP. ISCAS 2008: 3430-3433 - 2007
- [c13]Martin Radetzki, Rauf Salimi Khaligh:
Modelling Alternatives for Cycle Approximate Bus TLMs. FDL 2007: 74-79 - [c12]Rauf Salimi Khaligh, Martin Radetzki:
Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. IESS 2007: 313-324 - [c11]Martin Radetzki:
Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. MBMV 2007: 181-190 - 2006
- [c10]Martin Radetzki:
SystemC TLM Transaction Modelling and Dispatch for Active Object. FDL 2006: 203-209 - 2004
- [j3]Martin Schaaf, Andrea Freßmann, Rainer Maximini, Ralph Bergmann, Alexander Tartakovski, Martin Radetzki:
Intelligent IP retrieval driven by application requirements. Integr. 37(4): 253-287 (2004) - [c9]Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel:
Measurement of IP Qualification Costs and Benefits. DATE 2004: 996-1001 - [c8]Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki:
IPQ: IP Qualification for Efficient System Design. ISQED 2004: 478-482 - 2003
- [c7]U. Badelt, H. Kühl, Martin Radetzki:
sciPROVE: C++ Based Verification Environment for IP and SoC Design1. FDL 2003: 617-627 - 2002
- [j2]Martin Radetzki:
Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions). Informationstechnik Tech. Inform. 44(2): 99-102 (2002) - [c6]Ralf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, Peter Neumann, Jürgen Haase:
A Qualification Platform for Design Reuse. ISQED 2002: 75-80 - 2000
- [b1]Martin Radetzki:
Synthesis of digital circuits from object oriented specifications. University of Oldenburg, Germany, 2000, pp. 1-252
1990 – 1999
- 1999
- [c5]Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel:
Data Type Analysis for Hardware Synthesis from Object-Oriented Models. DATE 1999: 491- - 1998
- [j1]Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel:
A Unified Approach to Object-Oriented VHDL. J. Inf. Sci. Eng. 14(3): 523-545 (1998) - [c4]Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki:
ATM Cell Modelling using Objective VHDL. ASP-DAC 1998: 261-264 - [c3]Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel:
A Flexible Message Passing Mechanism for Objective VHDL. DATE 1998: 242-249 - [c2]Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel:
Übersetzung von Objektorientiertem VHDL nach Standard VHDL. MBMV 1998: 21-29 - 1996
- [c1]Guido Schumacher, Bernhard Josko, Gerhard Wagner, Martin Radetzki:
Development of a Telephone Answering Machine in a Lab - FPGAs in Education. FPL 1996: 400-404
Coauthor Index
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