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ORCIDJosé G. Delgado-Frias
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2020 – today
- 2022
[j34]Daniel Iparraguirre
, José G. Delgado-Frias, Howard Heck:
Asymmetric Crosstalk Harness Signaling for Common Eigenmode Elimination. IEEE Trans. Computers 71(9): 2048-2058 (2022)- [j33]Daniel Iparraguirre, José G. Delgado-Frias:
Asymmetric Crosstalk Harnessed Signaling for Large 3D Routing Integration. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1059-1063 (2022) - [c72]Daniel Iparraguirre, José G. Delgado-Frias:
ACHS Optimizations on 3D Interconnect Arrangements. ISCAS 2022: 1201-1202 - 2021
- [c71]Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck:
A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding. ISCAS 2021: 1-5 - 2020
- [j32]Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Yi Qian, Rahul Khanna:
Online Firmware Functional Validation Scheme Using Colored Petri Net Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1532-1545 (2020) - [j31]José Silva-Martínez, José G. Delgado-Frias:
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. 67-I(10): 3249-3250 (2020) - [j30]Michael A. Turi, José G. Delgado-Frias:
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 765-769 (2020)
2010 – 2019
- 2017
- [j29]Michael A. Turi, José G. Delgado-Frias:
Full-VDD and near-threshold performance of 8T FinFET SRAM cells. Integr. 57: 169-183 (2017) - [c70]Michael A. Turi, José G. Delgado-Frias:
An implemented, initialization algorithm for many-dimension, Monte Carlo circuit simulations using Spice. CCWC 2017: 1-4 - [c69]Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna:
Firmware functional validation using a Colored Petri Net model. MWSCAS 2017: 389-392 - 2016
- [j28]Johnathan Vee Cree, José G. Delgado-Frias:
Autonomous management of a recursive area hierarchy for large scale wireless sensor networks using multiple parents. Ad Hoc Networks 39: 1-22 (2016) - [c68]Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna:
A real-time UEFI functional validation tool with behavior Colored Petri Net model. MWSCAS 2016: 1-4 - 2015
- [c67]José G. Delgado-Frias, Zhe Zhang, Michael A. Turi:
Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance. ISCAS 2015: 2928-2931 - [c66]Rongyang Liu, José G. Delgado-Frias, Doug Boyce, Rahul Khanna:
UEFI USB bus initialization verification using Colored Petri Net. MWSCAS 2015: 1-4 - 2014
- [c65]José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger:
Welcome to MWSCAS 2014. MWSCAS 2014: 1-2 - [c64]Michael A. Turi, José G. Delgado-Frias:
An evaluation of 6T and 8T FinFET SRAM cell leakage currents. MWSCAS 2014: 523-526 - 2013
- [c63]Johnathan Vee Cree, José G. Delgado-Frias:
Management of large-scale wireless sensor networks utilizing multi-parent recursive area hierarchies. IGCC 2013: 1-6 - [c62]Zhe Zhang, José G. Delgado-Frias:
CNTFET 8T SRAM cell performance with near-threshold power supply scaling. ISCAS 2013: 2123-2126 - [c61]Zhe Zhang, José G. Delgado-Frias:
Near-threshold CNTFET SRAM cell design with gated cell power supply. MWSCAS 2013: 340-343 - 2012
- [c60]Zhe Zhang, Michael A. Turi, José G. Delgado-Frias:
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. ACM Great Lakes Symposium on VLSI 2012: 267-270 - [c59]Zhe Zhang, José G. Delgado-Frias:
CNTFET SRAM cell with tolerance to removed metallic CNTs. MWSCAS 2012: 186-189 - [c58]Jason Van Dyken, José G. Delgado-Frias:
A superscalar processor for a medium-grain reconfigurable hardware. MWSCAS 2012: 426-429 - [c57]Colby M. Gerik, Michael A. Turi, José G. Delgado-Frias:
FinFET 3T and 3T1D dynamic RAM cells. MWSCAS 2012: 454-457 - [c56]Johnathan Vee Cree, José G. Delgado-Frias, Mike Hughes, Brion Burghard, Kurt Silvers:
NOA: A Scalable Multi-Parent Clustering Hierarchy for WSNs. ANT/MobiWIS 2012: 1140-1145 - 2010
- [j27]Jason Van Dyken, José G. Delgado-Frias:
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm. J. Syst. Archit. 56(2-3): 116-123 (2010) - [c55]José G. Delgado-Frias, Zhe Zhang, Michael A. Turi:
Low power SRAM cell design for FinFET and CNTFET technologies. Green Computing Conference 2010: 547-553 - [c54]G. Ramirez-Conejo, Javier Díaz-Carmona, Agustín Ramírez-Agundis, Alfredo Padilla-Medina, José G. Delgado-Frias:
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters. ReConFig 2010: 406-411
2000 – 2009
- 2009
- [j26]Ruirui Guo, José G. Delgado-Frias:
IP Routing table compaction and sampling schemes to enhance TCAM cache performance. J. Syst. Archit. 55(1): 61-69 (2009) - [j25]Michael A. Turi, José G. Delgado-Frias:
Decreasing energy consumption in address decoders by means of selective precharge schemes. Microelectron. J. 40(11): 1590-1600 (2009) - [c53]Kylan Robinson, José G. Delgado-Frias:
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. ERSA 2009: 275-278 - 2008
- [j24]Peter Sapaty, Masanori Sugisaka, José G. Delgado-Frias, Joaquim Filipe, Nikolay N. Mirenkov:
Intelligent management of distributed dynamic sensor networks. Artif. Life Robotics 12(1-2): 81-87 (2008) - [j23]Li Zhao, José G. Delgado-Frias, Krishnamoorthy Sivakumar:
Performance analysis of multipath transmission over 802.11-based multihop ad hoc networks: a cross-layer perspective. IET Commun. 2(2): 380-387 (2008) - [j22]Michael A. Turi, José G. Delgado-Frias:
High-Performance Low-Power Selective Precharge Schemes for Address Decoders. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 917-921 (2008) - [j21]Mitchell J. Myjak, José G. Delgado-Frias:
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 14-23 (2008) - [c52]Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi:
FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA 2008: 311-312 - [c51]Michael A. Turi, José G. Delgado-Frias:
High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS 2008: 1464-1467 - 2007
- [j20]Peter Sapaty, Masanori Sugisaka, Robert Finkelstein, José G. Delgado-Frias, Nikolay N. Mirenkov:
Emergent societies: advanced IT support of crisis relief missions. Artif. Life Robotics 11(1): 116-122 (2007) - [j19]Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru:
Preface. Integr. 40(2): 61 (2007) - [j18]Mitchell J. Myjak, José G. Delgado-Frias:
Medium-Grain Cells for Reconfigurable DSP Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(6): 1255-1265 (2007) - [j17]Rongsen He, José G. Delgado-Frias:
Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distributed Syst. 18(12): 1727-1739 (2007) - [c50]H. Lin, José G. Delgado-Frias, Sirisha Medidi:
Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology 2007: 61-66 - [c49]H. Lui, José G. Delgado-Frias, Sirisha Medidi:
Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology 2007: 181-186 - [c48]R. Guo, José G. Delgado-Frias:
A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology 2007: 210-215 - [c47]Li Zhao, José G. Delgado-Frias:
MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM 2007: 941-945 - [c46]Rongsen He, José G. Delgado-Frias:
Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM 2007: 2763-2768 - [c45]Hongxun Liu, José G. Delgado-Frias, Sirisha Medidi:
Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. ICON 2007: 7-12 - [c44]Daniel R. Blum, José G. Delgado-Frias:
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS 2007: 2786-2789 - 2006
- [j16]Suryanarayana Tatapudi, José G. Delgado-Frias:
A mesochronous pipelining scheme for high-performance digital systems. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1078-1088 (2006) - [c43]Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias:
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. ERSA 2006: 123-129 - [c42]Rongsen He, José G. Delgado-Frias:
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM 2006 - [c41]Mitchell J. Myjak, José G. Delgado-Frias:
Superpipelined reconfigurable hardware for DSP. ISCAS 2006 - [c40]Suryanarayana Tatapudi, José G. Delgado-Frias:
A mesochronous pipeline scheme for high performance low power digital systems. ISCAS 2006 - [c39]Li Zhao, José G. Delgado-Frias:
Performance Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks. SECON 2006: 927-932 - [c38]Li Zhao, José G. Delgado-Frias:
Multipath Routing Based Secure Data Transmission in Ad Hoc Networks. WiMob 2006: 17-23 - [c37]Li Zhao, José G. Delgado-Frias:
On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications 2006 - 2005
- [j15]José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi:
Decoupled dynamic ternary content addressable memories. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2139-2147 (2005) - [c36]Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias:
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34 - [c35]Jin Liu, José G. Delgado-Frias:
DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES 2005: 97-103 - [c34]Mitchell J. Myjak, José G. Delgado-Frias:
A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164 - [c33]Suryanarayana Tatapudi, José G. Delgado-Frias:
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197 - [c32]Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias:
A distributed FIFO scheme for on chip communication. ISCAS (2) 2005: 1851-1854 - [c31]Suryanarayana Tatapudi, José G. Delgado-Frias:
A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI 2005: 282-283 - [e1]Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias:
Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-54-8 [contents] - 2004
- [c30]Andy Widjaja, José G. Delgado-Frias:
An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI 2004: 530-535 - [c29]Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias:
A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI 2004: 536-540 - [c28]Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias:
H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA 2004: 170-176 - [c27]Mitchell J. Myjak, José G. Delgado-Frias:
Pipelined Multipliers for Reconfigurable Hardware. IPDPS 2004 - 2003
- [c26]Fred L. Anderson IV, José G. Delgado-Frias:
A Reconfigurable Switch for a DSP Array. VLSI 2003: 3-6 - [c25]Mitchell J. Myjak, José G. Delgado-Frias:
A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27 - [c24]Daniel R. Blum, José G. Delgado-Frias:
A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI 2003: 58-64 - 2001
- [c23]José G. Delgado-Frias, Girish B. Ratanpal:
A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI 2001: 85-88 - [c22]Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov:
BASIS: A Biological Approach to System Information Security. MMM-ACNS 2001: 127-142 - 2000
- [j14]Stamatis Vassiliadis, Ming Zhang, José G. Delgado-Frias:
Elementary function generators for neural-network emulators. IEEE Trans. Neural Networks Learn. Syst. 11(6): 1438-1449 (2000) - [c21]José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan:
A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70 - [c20]José G. Delgado-Frias, Jabulani Nyathi:
A wave-pipelined CMOS associate router for communication switches. ISCAS 2000: 391-394
1990 – 1999
- 1999
- [j13]Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis:
A neuro-emulator with embedded capabilities for generalized learning. J. Syst. Archit. 45(14): 1219-1243 (1999) - 1998
- [j12]Chien-Ying Lu, José G. Delgado-Frias, Wei Lin:
A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybern. Syst. 29(2): 137-157 (1998) - [j11]Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis:
Executing tree routing algorithms on a high-performance pattern associative router. J. Syst. Archit. 44(11): 849-866 (1998) - [c19]Douglas H. Summerville, José G. Delgado-Frias:
Approaches for determining dynamic synchronization resource requirements. CATA 1998: 385-388 - [c18]José G. Delgado-Frias, Jabulani Nyathi:
A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI 1998: 59-64 - [c17]José G. Delgado-Frias, Richard Diaz:
A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI 1998: 128-133 - [c16]Adger E. Harvin III, José G. Delgado-Frias:
A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI 1998: 134-139 - 1996
- [j10]George Triantafyllos, Stamatis Vassiliadis, José G. Delgado-Frias:
Software Metrics and Microcode: A Case Study. J. Softw. Maintenance Res. Pract. 8(3): 199-224 (1996) - [j9]Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias:
Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers 45(9): 1045-1049 (1996) - [j8]Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis:
A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 7(5): 477-485 (1996) - [c15]Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville:
A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I 1996: 213-217 - [c14]José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville:
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251 - [c13]Valentine C. Aikens II, José G. Delgado-Frias, Steven M. Barber, Gerald G. Pechanek, Stamatis Vassiliadis:
A neuro-emulator with learning and virtual emulation capabilities. ICNN 1996: 1355-1360 - 1995
- [j7]Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias:
Flexible oblivious router architecture. IBM J. Res. Dev. 39(3): 315-330 (1995) - [j6]Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias:
The multi-associative branch target buffer: a cost effective BTB mechanism. Microprocess. Microprogramming 41(3): 211-225 (1995) - [c12]Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis:
A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106 - [c11]Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville:
A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems 1995: 238-242 - [c10]Adger E. Harvin III, José G. Delgado-Frias:
A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems 1995: 455-458 - 1994
- [j5]Chuan-Jen Chang, Stamatis Vassiliadis, José G. Delgado-Frias:
An investigation of binary CLA and ripple CMOS adder designs. Microprocess. Microprogramming 40(1): 1-21 (1994) - [c9]José G. Delgado-Frias, Rovy Sze, Douglas H. Summerville, Valentine C. Aikens II:
A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks. Great Lakes Symposium on VLSI 1994: 124-129 - [c8]Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis:
A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS 1994: 541-545 - [c7]Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias:
Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC 1994: 713-722 - 1993
- [j4]Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias:
Spin: the Sequential Pipelined Neuroemulator. Int. J. Artif. Intell. Tools 2(1): 117-132 (1993) - [c6]Gerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis:
A massively parallel diagonal-fold array processor. ASAP 1993: 140-143 - 1992
- [j3]José G. Delgado-Frias, Stamatis Vassiliadis, Jamshid Goshtasbi:
Semantic Network Architectures: an Evaluation. Int. J. Artif. Intell. Tools 1(1): 57-84 (1992) - [j2]Gerald G. Pechanek, Stamatis Vassiliadis, José G. Delgado-Frias:
Digital neural emulators using tree accumulation and communication structures. IEEE Trans. Neural Networks 3(6): 934-950 (1992) - 1991
- [c5]Robert H. Payne, José G. Delgado-Frias:
MPU: A N-Tuple Matching Processor. ICCD 1991: 225-228 - [c4]Nikolaos G. Bourbakis, Robin Williams, Forouzan Golshani, Myron Flickner, Ted Laliotis, Sukhan Lee, José G. Delgado-Frias, Dan Hammerstrom, Cris Koutsougeras, Gerald G. Pechanek, Benjamin W. Wah, John Yen, Farokh B. Bastani, Tom Cooper, Karan Harbison-Briggs, Rudy Lauber, Alun D. Preece, Imran A. Zualkernan, W. T. Tsai, Daniel E. Cooke, Martin S. Feather, Stephen Fickas, N. Minsky, Peter G. Selfridge, Douglas Smith:
AI in multimedia (panel session). ICTAI 1991: 3-12 - [c3]Stamatis Vassiliadis, Gerald G. Pechanek, José G. Delgado-Frias:
SPIN: a sequential pipelined neurocomputer. ICTAI 1991: 74-81
1980 – 1989
- 1989
- [c2]José G. Delgado-Frias, Will R. Moore:
A semantic network architecture for artificial intelligence processing. TAI 1989: 162-167 - 1988
- [j1]José G. Delgado-Frias, Will R. Moore:
Parallel architectures for AI semantic network processing. Knowl. Based Syst. 1(5): 259-265 (1988) - [c1]José G. Delgado-Frias, D. M. Green:
BVE: a wafer-scale engine for differential equation computation. ICS 1988: 101-107
Coauthor Index
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