"A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded ..."

Yannick Bonhomme et al. (2001)

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DOI: 10.1109/ATS.2001.990291

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258

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