"CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field ..."

Tetsuya Izu, Jun Kogure, Takeshi Shimoyama (2007)

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DOI: 10.1007/978-3-540-74735-2_25

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Tetsuya Izu, Jun Kogure, Takeshi Shimoyama:
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method. CHES 2007: 364-377

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