"A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis ..."

Yong-Suk Cho, Jae Yeon Choi (2012)

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DOI: 10.1007/978-3-642-35600-1_26

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Yong-Suk Cho, Jae Yeon Choi:
A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier. FGIT-GDC/IESH/CGAG 2012: 176-181

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