Abstract: An error-detecting 32-b reduced instruction set computer (RISC) designed in a 1.2- mu m CMOS technology with an on-chip watchdog using embedded ...

An error-detecting 32-b reduced instruction set computer (RISC) designed in a 1.2- mu m CMOS technology with an on-chip watchdog using embedded signature ...

ABSTRACT. This paper presents an error-detecting 32-bit RISC, designed in a 1.2µm CMOS technology, with an on-chip watchdog using embedded signature monitoring.

A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog. Ohlsson J., Rimen M., Gunneflo U.

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system, duplex with cold stand-by sparing, ...

A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog · Conference Paper. August 1992. ·. 22 Reads. ·. 93 Citations.

This work presents a campaign of fault injection to validate the Dependability of a fault tolerant microcomputer system. The system is duplex with cold ...

Fault injection for the formal testing of fault tolerance pp. ... A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog pp ...

A Study of the Effects of Transient Fault Injection into a 32-bit RISC with Built-in Watchdog. 316-325. Fault Injection. view. electronic edition via DOI ...

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by ...