Transmission conditional-sum (TGCS) adders realized in a standard 2.5- mu m CMOS technology are discussed. These adders offer short propagation delay and ...
It combines the conditional-sum addition logic with the transmission-gate logic design. The resulting adder has a very low delay time (i.e.. latency time is ...
Abstract: Transmission conditional-sum (TGCS) adders realized in a standard 2.5- mu m CMOS technology are discussed. These adders offer short propagation delay ...
Conditional-sum adders have been realized in a standard 2.5 ¿m CMOS technology. These adders offer short propagation delay and latency time (12.5 ns for 32 bit ...
Rothermel et al ., "Realization of transmission-gate conditional-sum (TGCS) adders with low latency time," IEEE Journal of Solid-State Circuits, vol. 24, no ...
Rothermel ei a/., "Realization of Transmission-Gate Conditional-Sum (TGCS). Adders with Low Latency Time," IEEE JSSC, Vol. 24, June 1989, pp. 558-561. [8] J ...
US6366943B1 - Adder circuit with the ability to detect zero when rounding
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Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time, T. Rothermel, et. al, IEEE Journal of Solid State Circuits, Vol. 24 ...
Rothermel et al., “Realization of transmission-gate conditional-sum. (TGCS) adders with low latency time," IEEE J. Solid-State Circuits, vol. 24, pp. 558-561 ...
Realization of transmission-gate conditional-sum (TGCS) adders with low latency time. 被引用文献2件. ROTHERMEL A. 収録刊行物. IEEE JSSC. IEEE JSSC 24 (3) ...
[2] Rothermel, A., et al., “Realization of Transmission-Gate Condi- tional-Sum (TGCS) Adders with Low Latency Time", IEEE J. Solid-. State Circuits, vol. 24 ...