VLSI Architectures for Real-Time Signal Processing

Abstract

Many real-time signal processing tasks require the ability to process very large amounts of data at very high throughput rates. In this report we present efficient special-purpose VLSI architectures for computing several real-time signal processing tasks including one dimensional Discrete Hartley (DHT) and Discrete Cosine transforms (DCT), multi-dimensional transforms, template matching and block matching.We first develop completely pipelined bit-serial systolic array architectures for computing one-dimensional DHT and DCT, when the number of sample points N is factorizable into mutually prime factors N1 and N2. We then develop a family of {em optimal} (as defined by VLSI complexity theory) architectures with area-time trade-offs for computing any (NxNx...xN) d-dimensional linear separable transforms. Finally we present semi-systolic linear array architectures for computing template matching and block matching, that are capable of handling the computations as well as the I/O bandwidth requirements efficiently.