A 13.3 ns double-precision floating-point ALU and multiplier
H Yamada, T Hotta, T Nishiyama… - Proceedings of ICCD …, 1995 - ieeexplore.ieee.org
H Yamada, T Hotta, T Nishiyama, F Murabayashi, T Yamauchi, H Sawamoto
Proceedings of ICCD'95 International Conference on Computer Design …, 1995•ieeexplore.ieee.orgOne-bit pre-shifting before alignment shift, normalization with anticipated leading'1'bit and
pre-rounding techniques have been developed for a floating-point arithmetic logic unit
(ALU). In addition, carry select addition and pre-rounding techniques have been developed
for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and
applied to the ALU and multiplier. These techniques reduced the delay time of the critical
path by 24%. Each unit was fabricated in 0.3/spl mu/m 2.5 V four-layer-metal CMOS …
pre-rounding techniques have been developed for a floating-point arithmetic logic unit
(ALU). In addition, carry select addition and pre-rounding techniques have been developed
for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and
applied to the ALU and multiplier. These techniques reduced the delay time of the critical
path by 24%. Each unit was fabricated in 0.3/spl mu/m 2.5 V four-layer-metal CMOS …
One-bit pre-shifting before alignment shift, normalization with anticipated leading '1' bit and pre-rounding techniques have been developed for a floating-point arithmetic logic unit (ALU). In addition, carry select addition and pre-rounding techniques have been developed for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and applied to the ALU and multiplier. These techniques reduced the delay time of the critical path by 24%. Each unit was fabricated in 0.3 /spl mu/m 2.5 V four-layer-metal CMOS technology and achieved a two-cycle latency at 150 MHz.
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