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100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Kouji FUKUDA Kouji NAKAHARA Hiroaki NISHI Publication IEICE TRANSACTIONS on Communications Vol.E89-B No.3 pp.696-703 Publication Date: 2006/03/01 Online ISSN: 1745-1345 DOI: 10.1093/ietcom/e89-b.3.696 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on the Next Generation Ethernet Technologies) Category: Keyword: Ethernet, MAN, skew, FEC, Full Text: PDF(1.8MB)>>
Summary: A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12  10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits10 lanes). One conveys forward error correction code ((132 b, 140 b) Hamming code), providing highly reliable (BER < 10-12) data transmission, and the other conveys parity data, enabling fault-lane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590 k gate circuit, which is small enough for implementation in a single LSI circuit. | |||||
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