Altitude SEE Test European Platform
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The Altitude SEE Test European Platform (ASTEP) [1] is a permanent mountain laboratory and a dual academic research platform created by Aix-Marseille University, CNRS and STMicroelectronics in 2004. The current platform, operated by IM2NP Laboratory [2], is dedicated to the problematic of Single Event Effect (SEE) induced by Terrestrial radiation (atmospheric neutrons, protons and muons) in electronic components, circuits and systems. Located in the French Alps on the desert Plateau de Bure at 2552m, in a low electromagnetic noise environment, the platform is hosted by the IRAM Observatory [3]. ASTEP is fully operational since March 2006.
Overview
Important dates
2004
The project of a permanent mountain laboratory dedicated to the issue of Single Event Effects (SEE) and Soft Errors (SE) in electronics is launched. The Plateau de Bure is retained as the future ASTEP location.
2005
2006
2007
2008
- Installation of the Neutron Monitor
2009
2010
2011
2012
References
Works cited
- Autran et al. “Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130nm SRAM”, IEEE Transactions on Nuclear Science, 2007, Vol. 54, n°4, p. 1002-1009.
- Autran et al. “Real-Time Neutron and Alpha Soft-Error Rate Testing of CMOS 130nm SRAM: Altitude versus Underground Measurements”, International Conference on IC Design & Technology, May 2008.
- Autran et al. “Altitude and Underground Real-Time SER Characterization of CMOS 65nm SRAM“. IEEE Transactions on Nuclear Science, Vol. 56, 2009, Vol. 56, N°4, p. 2258-2266.
- Autran et al. “Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level”, Microelectronics Reliability, 2010, Vol. 50, p. 1822-1831.
- Autran & Leray, Dossier thématique “Effets des radiations naturelles sur l’électronique au niveau atmosphérique et terrestre”, Revue de l’Electricité et de l’Electronique, Mars 2010.
- Autran et al. “Real-Time Soft-Error Rate Characterization of Advanced SRAMs”, in “Radiation Effects in Semiconductors”, Edited by K. Iniewski (CRC Press), 2010.
- Autran et al., “Real-Time Soft-Error Testing of 40nm SRAMs”, IEEE International Reliability Physics Symposium, Avril 2012, 3C-5.
