http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1203023-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b157d8840310718acba426a46a513374 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-527 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-507 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-556 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-76 |
| filingDate | 1983-10-03^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1986-04-08^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5a9bb2dd38e7eb4cc4221311d526ce3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90e0a15c9d73d5ffb92dc0d64d09f52a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f862f06c4a276c00e8032c65c873e798 |
| publicationDate | 1986-04-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1203023-A |
| titleOfInvention | Floating point microprocessor system |
| abstract | ABSTRACT OF THE DISCLOSURE A microprocessor integrated circuit includes a control, timing and interface section connected by control signal lines to each of the other functional elements. The section is further connected to a 16-bit wide internal information bus by a second bus. A third bus connects the section to a 16-bit wide external information bus. A buffer circuit connects the external informa-tion bus to the internal information bus. The internal informa-tion bus is connected by a fourth bus to a programmable shifter and unpacker section which is connected to a mantissa processor by a 64-bit wide fifth bus and by two 32-bit wide buses. The shifter is connected to an exponent processor by 16-bit wide buses. The mantissa processor is also connected to the internal information bus by a bus. The sign logic circuits are connected to the programmable shifter and unpacker section by a line. The mantissa processor includes a 32-bit arithmetic and logic unit (ALU), a variable width register file, working registers and flip-flops, control PLAs, detection logic and bus buffers. The exponent and sign processor includes a 16-bit wide ALU, variable width register file, working registers control and constants PLAs, detec-tion logic and sign logic and flipflops. The programmable shifter and unpacker is a 64-bit wide shifter capable of shifting in one machine cycle from 0 to 8 positions to the left or 0 to 24 positions to the right. The control, timing and interface section is based on a two-level microprogramming scheme to save microcode and to optimize execution times on a dynamic microcycle. |
| priorityDate | 1982-10-04^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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