http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1262492-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cceefacdcbabc92106fb8048d91a893d |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18 |
| filingDate | 1986-06-30^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1989-10-24^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_110a9874a41b0b3de4ce7c410a2d46f8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_406e9f48d621238af09fa34146f5f4e3 |
| publicationDate | 1989-10-24^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1262492-A |
| titleOfInvention | Computer memory apparatus |
| abstract | ABSTRACT OF THE DISCLOSURE A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of random access memory (RAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the read out of a pair of words from the preselected blocks of a single stack or adjacent stacks in tandem into a pair of subsystem data registers. For each memory read request, the words from each preselected pair of blocks are read out into the data registers in the same sequence providing a double fetch capability without any loss in performance. |
| priorityDate | 1985-07-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID49384 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID415726898 |
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