http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2121720-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6d44b4d59a56381632fd5e6c1c95749f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-362 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177 |
| filingDate | 1993-09-29^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ea2264f2f48cb0f8a467cfdb339172f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2faf18c39eebe7f53fc9921d229797bd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_198c4f83f6b9f36679e86255b5bf6997 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5fa821d3ee1009a74505c93d5af4007a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b765eba90b6eaead33848dc11a683aef |
| publicationDate | 1994-04-14^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2121720-A1 |
| titleOfInvention | Reservation overriding normal prioritization of microprocessors in multiprocessing computer systems |
| abstract | RESERVATION OVERRIDING NORMAL PRIORITIZATION OF MICROPROCESSORS IN MULTIPROCESSING COMPUTER SYSTEMS ABSTRACT Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device. |
| priorityDate | 1992-10-02^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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