http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101783168-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-413 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-227 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate | 2010-01-14^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-06-05^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f9e1c7a7ff55b2795852ea809fda0833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00e5979d1af7b89ab3877a27b9207997 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce7a570cfd663118de09b20c2965a0c1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5de2736db41acae529e920b5119bcfa7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed8339523e162597a8822edad811557b |
| publicationDate | 2013-06-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-101783168-B |
| titleOfInvention | Semiconductor integrated circuit device and operating method thereof |
| abstract | Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines (sl[0]-), a plurality of bit-lines (bt[0],bb[0]-), a plurality of ordinary memory cells (MEMCELL), an access control circuit (WD,CTRL), a plurality of sense-amplifiers (SA), first and second replica bit-lines (rplbt[0],[1]),, first and second replica memory cells (RPLCELL), and first and second logic circuits (INV0,1). The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits (INV0,1) are connected to the first and second replica bit-lines (rplbt[0],[1]), respectively; a sense-amplifier enable signal (sae) is generated from an output of the second logic circuit; and this signal (sae) is supplied to a plurality of sense-amplifiers (SA). |
| priorityDate | 2009-01-15^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID18526942 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426812071 |
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