| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78678 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2009-04-14^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-05-29^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75c6267d8c775da162e94c833c3742ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1f762358ce675ded84a52e9098365f4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98b6eff7f109c727e899f3faeecf82fc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31dacace61ed775968dc0980f99c636f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83a635e97e26d5017dc4c4b8a17c1dc9 |
| publicationDate |
2013-05-29^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-102007585-B |
| titleOfInvention |
Thin film transistor and method for manufacturing the same |
| abstract |
A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer. |
| priorityDate |
2008-04-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |