http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102971967-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0802 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0805 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G05F1-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-093 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G05F1-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L5-00 |
| filingDate | 2011-02-22^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2016-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-102971967-B |
| titleOfInvention | Digital frequency locked ring |
| abstract | For generating integrated circuit and the method for clock signal, this integrated circuit includes that (i) includes the FLL of voltage controlled oscillator, and this voltage controlled oscillator is configured to receive and controls input and generate by clock signal determined by this control input；(ii) microprocessor, it is configured to be powered and receive the clock signal generated by voltage controlled oscillator by supply voltage.Integrated circuit is configured so that supply voltage is as controlling to input, so that clock signal is determined by supply voltage. |
| priorityDate | 2010-02-23^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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