http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103930996-B

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-049
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-34
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
filingDate 2012-10-12^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-02-15^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2017-02-15^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-103930996-B
titleOfInvention Semiconductor device
abstract A MOSFET (1) is provided with: a substrate (10) comprising silicon carbide, being open on one principal-surface (10A) side thereof, and having a trench (19) formed therein that has a sidewall surface (19A); a gate-insulating film (21) formed so as to be in contact with the top of the sidewall surface (19A); and a gate electrode (23) formed so as to be in contact with the top of the gate-insulating film (21). The surface roughness within a square region located on the sidewall surface (19A) and being 100nm in length on a side is 1.0nm RMS or less.
priorityDate 2011-12-19^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419545355
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http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID6336889

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