http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105390477-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76894 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76888 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538 |
| filingDate | 2015-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-08-17^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105390477-B |
| titleOfInvention | A kind of multi-chip 3 D secondary encapsulation semiconductor devices and its packaging method |
| abstract | Present invention is disclosed a kind of multi-chip 3 D secondary encapsulation semiconductor devices and its packaging methods, including at least two mutually independent semiconductor devices, each semiconductor devices includes PCB substrate, at least one component is installed in the PCB substrate, the component connects the PCB substrate by conductor layer, three semiconductor devices are attached by interconnecting lead, and three semiconductor devices are also stacked integrally by adhesive phase；It is additionally provided with exit pad on the multi-chip 3 D secondary encapsulation semiconductor devices.Deft design of the present invention, it is simple in structure, by the way that multiple independent semiconductor devices with substrate are arranged, it can be in the fully enclosed preceding test individually tested each semiconductor devices and carry out comprehensive performance when three semiconductor devices connect, to ensure that the validity of product, avoid in the prior art must by three semiconductor devices it is fully enclosed after aptitude test, may caused by yield loss and the problems such as waste of material. |
| priorityDate | 2015-12-11^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419524915 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5352426 |
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