| abstract |
The present invention relates to a transistor device, an electronic device, and a method of forming a transistor device. Techniques are disclosed for forming transistor devices with reduced parasitic contact resistance relative to conventional devices. This technique can be implemented, for example, using standard contact stacks such as a series of metals on silicon or silicon germanium (SiGe) source/drain regions. According to one exemplary such embodiment, an intermediate boron-doped germanium layer is provided between the source/drain and the contact metal to significantly reduce contact resistance. Various transistor structures and suitable fabrication processes will be apparent from this disclosure, including planar and non-planar transistor structures (eg, FinFETs), as well as strained and unstrained channel structures. Graded buffers can be used to reduce misfit dislocations. These techniques are particularly suitable for implementing p-type devices, but can also be used for n-type devices if desired. |