http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106207492-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01Q1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01Q21-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01Q23-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01Q1-50 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01Q1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01Q23-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01Q21-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01Q1-50 |
| filingDate | 2016-08-28^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-06-28^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-06-28^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-106207492-B |
| titleOfInvention | High Density Integration integration tile style active phase array antenna framework |
| abstract | A kind of High Density Integration integration tile style active phase array antenna framework disclosed by the invention, it is desirable to provide a kind of volume is smaller, and weight is lighter, and cost is lower, and performance is stablized, and can eliminate self-excitation phenomena, the high tile style active phase array antenna framework of integrated level.The technical scheme is that: radiation array element layer is arranged on upper multi-layer PCB board (2), for each metal radiation patch (1) array module by radio-frequency feed electric wire (4) electrical connection mmic chip (5), mmic chip is encapsulated in the formation RF feed layer metal enclosed chamber (12) between multi-layer PCB board and lower multi-layer PCB board Nei；Each mmic chip is electrically connected channel element (7), power supply module (8) and wave beam control assembly (9) below the multilayer board (3) on baseplane, and with the radio frequency external interface (10) and control for being separately positioned on multilayer board bottom both ends, power external interface (11) formation DC power supply and control circuitry layer. |
| priorityDate | 2016-08-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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