| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02238 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28158
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02057
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7854
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02332 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-324 |
| filingDate |
2016-07-29^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-05-18^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-05-18^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-106409909-B |
| titleOfInvention |
Methods of manufacturing integrated circuit devices |
| abstract |
The present disclosure relates to methods of fabricating integrated circuit devices. An integrated circuit device may include a gate insulating layer covering a top surface of a fin-shaped active region and sidewalls opposite to each other, a gate electrode covering the gate insulating layer, and along an interface between the fin-shaped active region and the gate insulating layer Set of hydrogen atomic layers. A method of fabricating an integrated circuit device may include: forming an insulating layer covering a lower portion of a preliminary fin-shaped active region; forming a fin-shaped active region by annealing an upper portion of the preliminary fin-shaped active region in a hydrogen atmosphere, the fin-shaped active region having The source region has an outer surface with increased smoothness; and a hydrogen atomic layer is formed covering the outer surface of the fin-shaped active region. A gate insulating layer and a gate electrode may be formed to cover the top surface of the fin-shaped active region and sidewalls opposite to each other. |
| priorityDate |
2015-07-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |