http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109860198-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11529 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573 |
| filingDate | 2017-11-30^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-01-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-01-05^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-109860198-B |
| titleOfInvention | Memory element and manufacturing method thereof |
| abstract | The invention discloses a memory element and a manufacturing method thereof. The bottom insulating layer is located on the semiconductor substrate. The first conductive layer is a selective epitaxial growth layer and is located on the bottom insulating layer. A plurality of insulating layers is located over the bottom insulating layer. The second conductive layers and the insulating layers are stacked in a staggered mode and are electrically isolated from the first conductive layers. The contact plug penetrates through the bottom insulating layer and is electrically contacted with the semiconductor substrate and the first conducting layer. The channel layer is located on at least one side wall of the first through opening and electrically contacted with the contact plug, wherein the first through opening penetrates through the insulating layer and the second conductive layer to expose the contact plug to the outside. The memory layer is located between the channel layer and the second conductive layer. |
| priorityDate | 2017-11-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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