| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-2602
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0409 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-52 |
| filingDate |
2018-12-06^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2022-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-110415754-B |
| titleOfInvention |
Semiconductor systems, semiconductor chips and semiconductor memory systems |
| abstract |
The present invention provides a semiconductor system, a semiconductor chip, and a semiconductor storage system including the semiconductor system. The semiconductor system includes at least one semiconductor device of the first group and at least one semiconductor device of the second group. The semiconductor system includes a control block for receiving external addresses and providing internal addresses to the semiconductor devices of the first group and the semiconductor devices of the second group. The control block provides semiconductor devices from the first group with a first internal address corresponding to the external address, and the control block provides semiconductor devices from the second group with a second internal address that does not correspond to the external address. |
| priorityDate |
2018-04-26^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |