http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111415948-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78633 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1213 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-127 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1259 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1229 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1251 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78675 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78633 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-32 |
| filingDate | 2020-03-30^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-11-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111415948-B |
| titleOfInvention | Array substrate, display panel, display device and preparation method of array substrate |
| abstract | The invention discloses an array substrate, a display panel, a display device and a preparation method of the array substrate. It includes a substrate and at least one first thin film transistor; the first thin film transistor includes: a first gate; a first gate insulating layer on the side of the first gate away from the substrate; The first active layer on the side of the gate; the second gate insulating layer on the side of the first active layer away from the first gate insulating layer; the first active layer on the surface of the first active layer away from the first gate insulating layer a source electrode and a first drain electrode; a second gate electrode located on the side of the second gate insulating layer away from the first active layer; the first active layer includes a first region and a second region; the first gate electrode is on the backing The vertical projection on the bottom is within the vertical projection of the first region on the substrate; the vertical projection of the first region on the substrate is within the vertical projection of the second gate insulating layer on the substrate; the second gate insulating layer The vertical projection on the substrate is within the vertical projection of the first active layer on the substrate. |
| priorityDate | 2020-03-30^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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