http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111630744-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01H47-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H3-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01H83-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H3-22 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H9-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H9-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H9-041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02H3-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02H9-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02H9-06 |
| filingDate | 2019-01-18^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-12-20^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-12-20^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111630744-B |
| titleOfInvention | Arc suppression device and multi-stage arc suppression equipment |
| abstract | An arc suppression device is provided. The arc suppression device has a first terminal (1) and a second terminal (2), the terminals (1, 2) can be connected to a medium to high impedance alternating voltage source (AV), the arc suppression device comprises: a trigger circuit (B) , the trigger circuit is connected between the first terminal (1) and the second terminal (2) and is configured to output a trigger signal in response to exceeding a threshold voltage across at least one trigger element of the trigger circuit (B); the positive side signal circuit (C) and a negative side signal circuit (D), the positive side signal circuit and the negative side signal circuit are configured to output a positive clamp signal or a negative clamp signal respectively according to a positive voltage signal or a negative voltage signal input from the trigger circuit (B) bit signal; the positive side overvoltage clamping circuit (E) and the negative side overvoltage clamping circuit (F), the positive side overvoltage clamping circuit and the negative side overvoltage clamping circuit each include a first terminal ( 1) and the controllable semiconductor element (ES, FS) between the second terminal (2), the overvoltage clamping circuit (E, F) is configured so that when there is a clamping signal from the corresponding signal circuit (C, D) are configured to control their respective semiconductor elements (ES, FS) to be in a conduction state, and are configured to control their semiconductor elements (ES, FS) to be in a non-conduction state when there is no corresponding clamping signal for a predetermined period of time. |
| priorityDate | 2018-01-18^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Showing number of triples: 1 to 21 of 21.