| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7211 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0035
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0616
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2019-03-04^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06823699aba55601ed2ef07992a4084d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e8b4dfeb2091e383821485d167dd6bc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68249858d23e330658c3e38749c01044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3a708ff08a71fe6ca0a891330c91d41 |
| publicationDate |
2020-10-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-111771184-A |
| titleOfInvention |
Methods for detecting and mitigating degradation of memory media and memory devices using the same |
| abstract |
The present invention provides memory devices, systems, and methods of operation thereof. The memory device may include a non-volatile memory array and control circuitry. The control circuit may be configured to: store a value corresponding to a number of activation commands received at the memory device; update the value in response to receiving an activation command received from a host device; and in response to the A value exceeding a predetermined threshold triggers corrective action to be performed by the memory device. The control circuit may be further configured to: store a second value corresponding to a number of refresh operations performed by the memory device; update the second value in response to performing refresh operations; and in response to the value exceeding the first value. Two predetermined thresholds triggering a second corrective action performed by the memory device. |
| priorityDate |
2018-03-23^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |