http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112673427-B

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0088
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10
filingDate 2019-09-04^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2022-02-01^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2022-02-01^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-112673427-B
titleOfInvention Data state synchronization
abstract An example apparatus includes: a memory including a plurality of management units corresponding to respective groups of resistance variable memory cells; and a controller coupled to the memory. The controller is configured to perform a cleaning operation on a selected group of the memory cells and generate error correction code ECC parity data. The controller may be further configured to cause a write operation to be performed on the selected group of cells, thereby writing an inverted state of at least one data value to the selected group of cells and the ECC parity An inverted state of at least one of the verification data is written to the selected group of cells.
priorityDate 2018-09-11^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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