| abstract |
A technique for assembling multiple chips is disclosed. A plurality of chip layers are prepared, each chip layer including at least one chip die. Each chip block includes a plurality of electrodes that are assigned the same function. A plurality of chip layers are stacked sequentially in rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds sets of vertically arranged electrodes with displacement in the horizontal plane. For at least one group, vias are formed at least partially within the plurality of chip layers to expose vertically arranged electrode surfaces in the group. The through holes are filled with conductive material. |