| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-1204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0064
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-021
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 |
| filingDate |
2020-10-10^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_62f9cabcb38cd2b796360029cc92d626 |
| publicationDate |
2021-10-12^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113496738-A |
| titleOfInvention |
Memory device and method of operating the same |
| abstract |
Provided herein are memory devices and methods of operation thereof. The memory device may include: a memory block; a voltage generating circuit configured to operate in a first mode using an internal voltage to generate the operating voltage or a second mode using an external voltage to generate the operating voltage, and supplying the operating voltage to the memory block; and control logic configured to measure and store a first rise time for the operating voltage to rise to a target level in the first mode, and to control the voltage generating circuit to cause a first rise time for the operating voltage to rise to the target level in the second mode The second rise time is equal to or longer than the first rise time. |
| priorityDate |
2020-04-07^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |