| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_355555c24076b659de494363997bd57d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78672
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 |
| filingDate |
2020-08-26^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9f64b8db87219a953db5526cf16a425b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a33dbd3de45c541de1aa5b78fcab5c0c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f10aa943ecd22e81fb10ca5815aeba07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f185805bd9f628248a8c2a237c72bff |
| publicationDate |
2022-04-08^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-114303242-A |
| titleOfInvention |
Memory device with two-transistor memory cell and access circuit board |
| abstract |
Some embodiments include apparatus and methods using a substrate, pillars having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, located between the first conductive plate and the second conductive plate and a memory cell electrically separated from the first conductive plate and the second conductive plate, and conductively connected. The first conductive plate is located in a first level of the apparatus and is separated from the pillars by a first dielectric located in the first level. The second conductive plate is located in a second level of the device and is separated from the struts by a second dielectric located in the second level. The memory cell includes a first semiconductor material in a third level of the device between the first level and the second level and in contact with the pillars and the conductive connection, and in the first level A second semiconductor material in a fourth level of the device between a level and the second level and in contact with the pillars. |
| priorityDate |
2019-08-28^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |