http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102006008503-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_69a4ae662cd6a46490ee45a70e85dc39 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76888 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2006-02-23^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2014-02-13^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b140dcc6deee95c6e3b1411dd7cf2615 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65dab76f8b8d8ec71aee6d05cae78df6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27d1bc73a404bf41c51b5a833455f07d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7e8c77718c8d80ec207b05ffa1d6dca http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_463feef11f0612baaf582725c2bbb8ad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_361d67a7c821d6236e970b42bc5b370b |
| publicationDate | 2014-02-13^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102006008503-B4 |
| titleOfInvention | Method for producing nonvolatile memory cells |
| abstract | A method of manufacturing nonvolatile memory cells, the method comprising: - providing a semiconductor wafer (2), wherein the semiconductor wafer (2) comprises a semiconducting substrate (14) having a surface; - applying a structured charge trapping layer (16) on the surface of the semiconductor wafer (2); - depositing a plurality of gate lines (28) on the structured charge trapping layer (16); - forming a plurality of buried bit lines (8) between the gate lines (28), each of the buried bit lines (8) being embedded in the semiconducting substrate (14); - depositing a first insulating layer (38) in the region between the plurality of gate lines (28) and the patterned charge trapping layer (16); - etching the first insulating layer (38) to form first contact holes (40), the first contact holes (40) extending from the surface of the first insulating layer (38) to the surface of the buried bit lines (8); - applying an insulating intermediate layer (44) on the side walls of the first contact holes (40); Depositing a contact filling material (46) into the first contact hole (40), wherein the contact filling material (46) contacts the first contact holes (40) from the surface of the buried bit lines (8) to a predetermined height in the first contact holes (40); 40) fills; - applying a further insulating intermediate layer (48) on an upper side of the contact filling material (46) so that the contact filling material (46) above the buried bit lines (8) is completely surrounded by insulating layers (44; 48); Depositing a second insulating layer (60) over the surface of the semiconductor wafer; Etching the second insulating layer (60) and the second insulating intermediate layer (48) to form second contact holes (70), wherein the second contact holes (70) extend from the surface of the second insulating layer (60) to the surface of the contact Extend filling material (46); and Forming a contact plug by filling the second contact holes (70) with a conductive material. |
| priorityDate | 2005-12-20^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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